
Timeline
About me
ASIC Design Engineer (RTL| UCIe | ARM| SoC | Ethernet | Architecture Design)
Education

Shanthiniketan school
2017 - 201812th pcm with computer 91.4%
College of engineering, trivandrum
2019 - 2023Bachelor of technology - btech applied electronics and instrumentation
Experience

Netrasemi
Sept 2022 - nowi) Design of ARM based SoCii) IP designing iii) Ethernet Development iv) UCIe i)UCIeii) Designed and integrated AVB protocol into ethernetiii)FPGA verification
ASIC Design Engineer
Oct 2023 - nowDigital Design intern
Sept 2022 - Sept 2023
Licenses & Certifications
- View certificate

Digital systems : from logic gates to processors
Universitat autònoma de barcelona - View certificate

Introduction to css3
University of michigan - View certificate

Aircraft maintenance
Nptel - View certificate

Introduction to html5
University of michigan - View certificate

Interactivity with javascript
University of michigan - View certificate

The evolving universe
Caltech - View certificate

Introduction to electronics
Georgia institute of technology
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