Wan-Yu Wu

Wan-Yu Wu

Teaching Assistant

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location of Wan-Yu WuMountain View, California, United States

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  • Timeline

  • About me

    Analog/Mixed-Signal IC Design and Layout Engineer

  • Education

    • National University of Tainan

      2017 - 2019
      M.S. Electrical Engineering GPA 3.85/4.0

      Publication: Design an Asymmetrical Rectangular Structure by Waveguide Polarization Conversion, International Conference on Advanced Technology Innovation (ICATI accepted), 2019Thesis: Optimized Design of a Refractive Index Sensor based on Waveguide Polarization Conversion Effect利用波導極化轉換效應之折射率感測器的優化設計https://hdl.handle.net/11296/ubz527

    • National University of Tainan

      2013 - 2017
      Bachelor of Science - BS Electrical Engineering

      Ministry of Science and Technology College Student Research Grant 國科會大專生研究計畫: 3DES 結合混沌同步來提升系統運算

  • Experience

    • National University of Tainan

      Sept 2018 - Jun 2019
      Teaching Assistant

      - Control Systems, 2019- Signals and Systems, 2018- Linear Algebra, 2018

    • INNOLUX群創光電

      Aug 2019 - Jul 2021
      Display design Engineer

      · Led and delivered 3 products: 5” photo sensor embedded TFT-LCD, 55+” rollable AM mini-LEDtouchscreen display, and 34” mini-LED vehicle infotainment display for 2023 Cadillac Lyriq EV.· Designed driver ICs and conducted simulations to validate stack-up circuit designs for AM displaysusing TFT technology.· Designed and verified pixel, panel, and photomask layouts for OLED, LCD, and mini-LED displaysusing Virtuoso, AutoCAD, and MATLAB for functionality, performance, and manufacturability.· Supervised the prototype manufacture flow, conducted test analysis on prototypes, and resolved failures such as burn-in effect, dead and stuck pixels, and signal integrity issues.· Delivered projects on time through leadership, collaboration, and proactive planning. Show less

    • MediaTek

      Jul 2021 - Sept 2023
      Analog/Mixed-Signal IC Design and Layout Engineer

      · Taped out 6 full-chip designs across various processes, including TSMC's 3/7nm FinFET, TSMC's12/22/28nm, UMC's 22/28nm, and Intel's 16nm (sign-off only).· Conducted block-level verification in mixed-signal design, ensuring compliance with power, timingclock, and area specifications through EDA tools such as Virtuoso and Laker.· Designed logic, floorplan, routing, and building blocks such as DDR4/5, PLL, DAC, LDO, and ADC.· Ran customized verification checks (DRC, LVS, PERC, ERC, antenna) on Calibre, and conductedsimulations for latch-up, noise analysis with Voluts, and PDN optimization for reliability.· Collaborated seamlessly with international teams across Boston, Shanghai, Singapore, and India. Show less

    • CHPT

      Jul 2024 - now
      PCB Circuit Design and Layout Engineer
  • Licenses & Certifications

    • Circuit Simulation and Analysis with HSPICE

      National Chip Implementation Center, Taiwan Semiconductor Research Institute
      View certificate certificate
    • Cell-Based IC Physical Design and Verification with Innovus

      National Chip Implementation Center, Taiwan Semiconductor Research Institute
      Jan 2018
    • RF CMOS IC Design

      National Nano Device Laboratories, Taiwan Semiconductor Research Institute
      Jan 2018