Keng Kooi Lim

Keng Kooi Lim

Backend Assembly and Testing Principle Engineer

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location of Keng Kooi LimDraper, Utah, United States

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  • Timeline

  • About me

    New Product and HVM Product Manager at Intel | Testing | YIELD, REL Improvement | New Product Qualification | Pre and Post Si Validations | Tape Development | NPI Program Lead | Wafer fab and Assembly Manufacturing

  • Education

    • National University of Singapore

      -
      Master of Science - MS Major in the Semiconductor
    • Nanyang Technological University

      -
      Bachelor Degree of EEE Electrical and Electronics Engineering
  • Experience

    • Micron Technology

      Aug 2002 - Feb 2010
      Backend Assembly and Testing Principle Engineer

      Product Lead, working on the memory DRAM and Nand MomoryKey responsible included:- Backend yield improvement, electrical failure analysis, communication with FAB to improve backend yield.

    • IM Flash

      Mar 2011 - Jan 2015
      Fab Manufacturing Principle Product and REL Engineer Lead

      Working on 2D Nand, 3D Nand and the 3D XPoint Memory Products.Product lead, responsible included Product Yield Improvement, Solving REL issue, New Product Qualification, process deviation disposition, training.Awarded Best Product and REL Technical Lead in the company

    • Intel Corporation

      Dec 2015 - Jun 2017
      Fab Product Manager

      Startup new 3D Nand Wafer Fab Manufacturing in Intel Dalian, China. Setup new Fab Product team in the 3D Nand Fab.Solve 3D Nand Product, Yield and REL issue and qualify 3D nand product.

    • Intel Corporation

      Aug 2018 - now
      Director New Product Development

      • Leading Product and TEst organization with groups 40 engineers globally (from USA, China Dalian, Shanghai), with 3 senior managers direct report. • Set up Fab Product Technology Development organization from the green field. Experienced in recruiting and growing world-class teams.• Key responsibilities of the organization are the Sort tape development, Pre and Post Si debug, design validation, Pre-Si simulation, Sort Test Time Reduction, Yield/REL improvement/debugging and product qualification and ramping activities.• Successfully ramping 3 technology nodes, 5 products, 7 test chips in the past 5 years with a good track record help team members, supervisors, companies, and customers success.• Selected as Intel Excellent Manager Award in 2022. Show less

  • Licenses & Certifications