Bastien Desalle

Experience

• 

  Uniways

  Jun 2010 - Aug 2010

  Intern

  Porting video analysis algorithms on an OMAP3 platform. working on a beagle board. Optimized code using assembly code instead of C

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  Toshiba Medical Research Institute USA, Inc. (TMRU)

  Nov 2011 - Sept 2014

  • FPGA/ASIC Engineer

    Feb 2014 - Sept 2014

  • Associate FPGA/ASIC Engineer

    Nov 2011 - Feb 2014
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  Anova Technologies

  Sept 2014 - Apr 2018

  FPGA Developer

  Low-latency exchange connectivity switch: Simultaneous delivery of redundant data over wireless (millimeter wave technologies (Eband) or Free Space Optics) and Fiber. These two mediums complement each other to ensure best performance at all time (low latency and availability). • Chopping Algorithm : Implemented proprietary patent-approved chopping algorithm. This design allows multiple clients (1G Ethernet) to transmit over a single media (1G Ethernet) . Worked on specification and architecture design for updated version on Kintex Ultrascale device using different algorithm.• Worked on transceiver implementation optimization in order to lower latency.• Designed IP: I2C with clock stretching support, 8B10B, 1G Ethernet, 1G Layer 2 Loopback. Show less

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  Nokia

  May 2018 - Feb 2021

  SOC / FPGA Engineer

  5G L1 FPGA Design / Verification Hardware Verification Leader (1 year): Responsible for 5G Transmitter side Hardware Verification. FPGA Verification (1 year): Responsible for verification of 5G Receiver submodule (RX Status). while managing code coverage for the whole project and managing the resolution of bugs found in the design. Fault Coordinator(3 Months): Responsible for Managing and Leading team of Designer/ Verification people in order to solve Priority Blocker for 5G Receiver. Show less

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  Atos

  Feb 2021 - now

  Product Quality and Reliability Manager