Deep Enrich
Sajjad Ahmed
Intern
2000 followers
Karāchi, Sindh, Pakistan
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About me
ASIC RTL Design Engineer | RA@MERL-UIT | Co-mentor GSOC '22 | aws-fpga | System verilog | RISCV | Physical Design | Cadence
Education
FG Boys Inter College
-Intermediate Pre-Engineering AFG Public School
2013 - 2015Matric Biology, General A
Usman Institute of Technology
2017 - 2021Electrical Engineering Computer Engineering A+
Experience
Brandmefy
Jan 2019 - May 2022Intern
Micro Electronics Research Lab
Jul 2019 - Jan 2024Research Associate
Feb 2022 - Jan 2024Research Assistant
Oct 2021 - May 2022Research Intern
Jul 2019 - Oct 2021
Barcelona Supercomputing Center
Jan 2024 - nowResearch Engineer (FPGA)
Feb 2025 - nowJunior Research Engineer
Jan 2024 - Feb 2025
Licenses & Certifications
- View certificate
Genus Synthesis Solution with Stylus Common UI v20.1 Exam
Cadence Design SystemsAug 2021
- View certificate
Basic Static Timing Analysis v1.2 Exam
Cadence Design SystemsApr 2021
Languages
- chChinese (mandarin)
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