James Salas

Experience

• 

  Intel Corporation

  Oct 2005 - Aug 2008

  Product Development Engineer

  - Product Yield for Itanium Processors- Data analysis for test program development- Yield analysis for establishing priorities- Validation of failure bins

• 

  Emerson Process Management

  Aug 2008 - Jan 2011

  Safety Instrumented Systems Engineer

  - Lead for the Costa Rica Team- Managed ESD and BMS SIS projects- Implementation of the Simulation System for local office- Project lead for several control automation projects

• 

  Hewlett Packard Enterprise

  Feb 2011 - now

  Lead the FPGA/CPLD engineering team overseeing design, verification and quality system management solutions. Started working in CPLD/FPGA verification using SV and VMM for developing simulation environments. Started an early engagement in UVM and transition as main verification methodology. Focused several years in static tools to aid verification (QuestaCDC, HAL).After 5 years in the role, move to FPGA design tasks using Verilog/SystemVerilog. Gained experience using several vendor tools like Lattice Diamond and Quartus.

  • Engineering Manager

    Apr 2020 - now

  • VLSI/FPGA Engineer

    Feb 2011 - Apr 2020