Talk to sales Try for Free
Gabriel Caffarena

Gabriel Caffarena

Computer Programmer/Research Technician

Followers of Gabriel Caffarena1000 followers
location of Gabriel CaffarenaMálaga, Andalusia, Spain

Connect with Gabriel Caffarena to Send Message

Connect

Connect with Gabriel Caffarena to Send Message

Connect

  • Timeline

  • About me

    Open RAN Chip Development Manager at Vodafone (_VOIS). Honorary Fellow Universidad CEU San Pablo. ASIC/FPGA/GPU/MCU. Music Composition

  • Education

    • Conservatorio Superior de Música de Málaga

      1986 - 1993

    • Universidad de Málaga

      1991 - 1998
      MSc

    • Imperial College London

      2004 - 2004
      PhD Training

    • Universidad San Pablo-CEU

      2012 -
      Bachelor's degree

    • Universidad Politécnica de Madrid

      2001 - 2008
      Ph.D.

  • Experience

    • University College London

      Jun 1998 - Sept 2000
      Computer Programmer/Research Technician

    • Imperial College London

      Oct 2000 - Sept 2001
      Network Support Engineer

    • Universidad Politécnica de Madrid

      Oct 2001 - Jan 2010

      • Assistant Professor

        Nov 2005 - Jan 2010

      • PhD Student

        Oct 2001 - Oct 2005

    • Imec

      Jul 2002 - Aug 2002
      Visiting Researcher (predoctoral)

    • Imperial College London

      Jul 2004 - Sept 2004
      Visiting researcher (predoctoral)

    • Universidad CEU San Pablo

      Feb 2010 - now

      • Honorary Fellow

        Apr 2023 - now

      • Coordinator of Master in Biomedical Engineering

        Sept 2017 - Apr 2023

      • Profesor Titular (acreditado ANECA) - Associate Professor

        Feb 2010 - Apr 2023

    • Universidad de Málaga

      Aug 2010 - Aug 2010
      Visiting Researcher

    • ENSSAT, Université de Rennes 1

      Aug 2012 - Aug 2012
      Visiting Researcher

    • INSA Rennes

      Jul 2013 - Jul 2021
      Visiting Professor

    • Freelance

      Jan 2016 - now
      Music Composer

    • University of Oxford

      Jul 2016 - Jul 2016
      Visiting Researcher

    • _VOIS

      Apr 2023 - now
      Open RAN Chip Development Manager

  • Licenses & Certifications

    • Acreditación Profesor Universidad Privada

      ANECA
      Jun 2024

    • Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

      Udemy
      Feb 2024
      View certificate certificate

    • Energy Efficiency in Open RAN Learning Program

      Telecom Infra Project
      Aug 2024
      View certificate certificate

    • Acreditación Profesor Contratado Doctor

      ANECA
      Jun 2024

    • Why Open RAN? Learning Program

      Telecom Infra Project
      May 2024
      View certificate certificate

    • Certificate of Proficiency in English (CPE)

      University of Cambridge
      Jan 2005

    • Acreditación Profesor Titular de Universidad (Ing. Telecomunicación)

      ANECA
      Jul 2024

    • Generative AI Overview for Project Managers

      Project Management Institute
      May 2024
      View certificate certificate

    • Open RAN Fundamentals Learning Program

      Telecom Infra Project
      Feb 2024
      View certificate certificate

    • CCNA

      Cisco
      Jan 2000

  • Honors & Awards

    • Awarded to Gabriel Caffarena
      Acreditación Profesor Titular ANECA Sep 2024
    • Awarded to Gabriel Caffarena
      Best Science Difusion Activitivy 2022 - USP-CEU "Rehabilitation, virtual reality, robotics and oncopediatrics" Universidad San Pablo CEU Jun 2023
    • Awarded to Gabriel Caffarena
      Best Teaching Innovation Project 2018 USP-CEU "Cognitive disability in the University" Universidad San Pablo CEU Sep 2020
    • Awarded to Gabriel Caffarena
      Best Teaching Quality Degree 2018 USP-CEU - Degree in Biomedical Engineering Universidad San Pablo CEU Feb 2020
    • Awarded to Gabriel Caffarena
      Best Paper Award (IADIS CGVCVIP 2013) - Jul 2013 "NEW RADIX-2 AND RADIX-2^2 CONSTANT GEOMETRY FAST FOURIER TRANSFORM ALGORITHMS FOR GPUS", Sreehari Ambuluri, Mario Garrido, Gabriel Caffarena, Jens Ogniewski, Ingemar RagnemalmIADIS Computer Graphics, Visualization, Computer Vision and Image Processing 2013 (CGVCVIP 2013); 07/2013
    • Awarded to Gabriel Caffarena
      UPM Best PhD Thesis Universidad Politécnica de Madrid Jan 2011 "Combined Word-Length Allocation and High-Level Synthesis of DSP Circuits"Universidad Politécnica de Madrid2008
    • Awarded to Gabriel Caffarena
      Angel Herrera Research Award 2012, Honourable Mention University CEU San Pablo 2011
    • Awarded to Gabriel Caffarena
      IEEE Senior Member IEEE 2011
    • Awarded to Gabriel Caffarena
      Quality Paper Award (ReConfig'04) International Conference on Reconfigurable Computing and FPGAs 2004 “Generation of High-Speed Parameterized Floating-Point Units”G. Leyva, G. Caffarena, C. Carreras, O. Nieto-Taladriz. International Conference on Reconfigurable Computing and FPGAs ReConFig'04, Colima (Mexico), September 2004