Dimuthu Jayawardane

Experience

• 

  Dialog Axiata PLC

  Aug 2016 - Dec 2016

  Engineering Trainee

  Dialog Axiata PLC was an exciting and challenging internship opportunity to apply my theoretical knowledge that I have gathered from university and other places and the practical experience gained from project involvement in the real world telecommunication engineering field.

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  Synopsys Inc

  Feb 2018 - Dec 2022

  •Contributed as a Product validation Engineer for VC LP (Static Low Power sign-off tool by Synopsys) which involves Customer support, Root cause analysis of customer issues, Project management (JIRA) and Test plan review.•Validated more than 300 bugs and enhancements of VC LP tool related to Power Intent Consistency Checks, Architectural Checks, Structural and Power and Ground (PG) Checks, and Functional Checks across multiple stages of the design flow, including RTL, netlist, and PG netlist levels•Conducted Sign-off Abstract Model Validation to provide faster low power sign-off and improved performance without any loss of accuracy or quality of results.•Created and reviewed comprehensive test plans and test cases.•Provided critical support for field Application Engineers during release migrations for Apple, Intel, Socionext, Renesas and Toshiba. This included assisting with the transition to new software versions, ensuring smooth upgrades, and troubleshooting any issues that arose during the migration process.• Engaged in analyzing tool issues reported by customers. This involved close collaboration with development teams to implement fixes and enhancements.•Directly worked with on-site customer application engineers to understand customer specific needs and requirements. Provided tool enhancements and validated them.•Reviewed specifications and user guides to ensure customer requirements were met and to ensure industrial documentation guidelines are met.•Maintained regression test suites and wrote automation scripts for effective bug detecting.•Developed python scripts for analyzing tool release to release checker report differences.•Automated VC LP release patch JIRAs follow up using a python script. Show less

  • Application Engineer Sr I

    May 2022 - Dec 2022

  • Application Engineer II

    Feb 2020 - May 2022

  • Application Engineer I

    Feb 2018 - Feb 2020
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  X-EPIC

  Dec 2022 - now

  Senior Product Engineer

  • Developed UVM testbench for RTL designs: During the creation of an in-house test case pool for flow and performance testing of a simulation tool, I was assigned to build UVM testbenches for AXI Memory Design and ALU design to cover all scenarios and test combinations.•Power Aware Simulation Testing: Performed critical power-aware simulation testing for key Unified Power Format (UPF) LRM commands.•Memory Testing on Emulation Platform: Conducted memory testing for different memory synthesis directives (Distributed RAMs, Block RAMs, Ultra RAMs and Registers).•Verified advanced memory optimization options and memory merging techniques in XEPIC's hardware flow.•Validated different XEPIC HuaPro memory partitioning strategies to optimize system performance and resource utilization.•Tested extensive support for third-party netlists in the HuaPro emulation and prototyping environment.•Validated XEPIC simulation and emulation platform using four Open Source RISCV SoCs (OpenPiton, Hummingbirdv2 E203, Amber, Black-parrot) ensuring functionality and performance.•Developed Amber SoC as a target reference design covering RTL simulation, Logic Synthesis, Hardware Compilation, Place & Route and Emulation Run in XEPIC Hardware flow by modifying the RTL code. Created a complete document including all the RTL modifications and run steps.•Developed C programs for multi-core OpenPiton RISC-V SoC (up to 64 cores) for testing parallel simulation feature.•Integrated Xilinx IPs (DDR4 Memory, UART) into OpenPiton design, enhancing communication and memory management.•Demonstrated integrating Xilinx IPs (DDR4 Memory, UART) and utilizing the XEPIC DDR (DDR4) daughter board solutions for extensive memory access.•Developed a AXI Memory to integrate with AXI Interconnect module. Provided OpenPiton+ AXI Interconnect+ AXI Memory ecosystem to the customer, enabling their IP integration.•Created and maintained a Git-based version control system for managing OpenPiton design. Show less