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Manoj Pandya

Manoj Pandya

Design Engineer

Followers of Manoj Pandya358 followers
location of Manoj PandyaPortland, Oregon, United States

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  • Timeline

  • About me

    Sr. Asic Design Engineer at Intel

  • Education

    • High School

      -

    • California State University-Northridge

      1991 - 1994
      Master of Science (MS) EE

    • Sardar Patel University

      -
      BS Electrical and Electronics Engineering

  • Experience

    • Sharp Microelectronics

      Oct 1994 - Aug 2000
      Design Engineer

    • PMC-Sierra

      Aug 2000 - Jul 2007
      Leader, Product Development

    • Cypress Semiconductor

      Aug 2007 - Jul 2010
      Principal Design Engineer

    • PMC-Sierra

      Jul 2010 - Jul 2013
      Tech Leader , Product Development

    • Intel

      Jul 2013 - now
      Sr. Asic Design Engineer

  • Licenses & Certifications