Andrew Neely

Experience

• 

  Unisys (Borroughs)

  Jul 1986 - Jul 1995

  Senior Electrical Engineer

  Electronic development of mainframe computer systems,

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  Avago Technologies

  Jul 1995 - Nov 2014

  Senior hardware engineer

  Avago technologies - formerly, LSI, Agere Systems, Lucent technologies, AT&T Bell labs.Design Implementation of base station ASSPs.Design of standard product and ASIC communication SOCs with high-speed (10GHz) serdes, DDR3, and GPIO interfaces. Responsibilities include SOC design from RTL synthesis (Synopsys DC, DCXP) to Prototype debugging. Implement both top level and block level designs. Work with front end designers; handling netlist edits for functional changes using Conformal for some ICC ecos; timing closure; clock network design; guiding place and route personnel; some place and route (ICC) experience; static timing analysis (Primetime DMSA); timing simulations (Verilog); netlist audits, formal verification; DFT, scan and memory BIST insertion, vector generation (DFTA, fastscan) and verification. This type of work requires organized individuals as well as coordinated team work. I am experienced writing makefiles, Unix kshell, Nawk, Sed, TCL, and Perl scripts to automate processes, enhance productivity and reduce errors. Additional responsibilities include; Interfacing with customer, using design checklists, documenting design flows, methodology, and results on internal web pages; package pin out, spice simulation of critical interfaces and circuits; ground bounce analysis; Show less

• 

  Intel Corporation

  Nov 2014 - now

  Intel acquired the network processor division of Avago technologies - formerly, LSI, Agere Systems, Lucent technologies, AT&T Bell labs. The network processor division is largely intact, and my job is exactly the same as described below.

  • Retired

    Jan 2023 - now

  • Design Engineer

    Nov 2014 - now