Sharmila Devi Kamatchi

Experience

• 

  Bharat Electronics Limited

  Feb 2000 - Feb 2001

  Graduate Apprentice Trainee

  One year Graduate Apprenticeship Trainee

• 

  VDesign Private Limited

  Jan 2001 - Jan 2002

  Engineer

  RTL, Synthesis & PAR of sample design forFPGA Evaluation Kit, and various (Xilinx, Altera/ Actel) daughter add-on cards for Vdesign Rapid ASIC Prototype System

• 

  SRM University

  Jan 2002 - Jan 2004

  Lecturer
• 

  CMC Limited

  Oct 2004 - May 2005

  Engineer

  Xilinx FPGA based Protoype design of Substation Automation

• 

  GDA Technologies

  Jun 2005 - Dec 2007

  Senior Engineer

  FPGA Design Engineer - Design of UTOPIA Interface of a ATM based FPGA Prototype - Fujitsu - JapanDesign of Hard-Soft Register Interface, Address Decoder of a HDLC based FPGA Prototype - Fujitsu - JapanC++ Model based Verification of AES through FLI - In-house GDAC Model based Verification of AES through PLI - In-house GDA

• 

  L&T Infotech

  Jul 2007 - May 2012

  Senior Engineer

  FPGA Design Engineer :-Altera FPGA NIOS based Emulation of MIPI-CSI2 IP of 3D Image Sensor SoC, OVM based Block level Verification of MCM, ACM blocks of an Telecom SoC, Design of Microblaze based Memory Controllers and PLB Bridge in Virtex6 FPGA based Prototype, Design & Validation of Spartan 3A FPGA Evaluation Kit

• 

  Qualcomm

  May 2012 - Jan 2013

  Contract Employee

  Pre-Silicon Emulation :-Xtensa based Synopsys USB3.0 Device Controller on HAPS 62, MIPS based Chipidea USB2.0 HOST Controller on HAPS 54, Post Silicon Validation of MIPS based Chipidea USB2.0 OTG Controller

• 

  CDOT Alcatel Lucent Research Centre

  Feb 2013 - Aug 2014

  Technical Lead

  WiMax Base Station & CPE Design on ArriaII-FPGA - CPRI IP config, design

• 

  HCL Technologies

  Aug 2014 - Jul 2018

  Senior Technical Lead

  Hands-on experience in Design of IEC61850, EtherCAT protocols using Zynq US+ SoC FPGA

• 

  Mirafra Technologies

  Aug 2018 - Dec 2018

  Member Of Technical Staff

  Worked as a sub-contractor for 5G UE test FPGA Development at NOKIA Networks

• 

  Nokia

  Jan 2019 - now

  Managing a team of talents skilled in ASIC Design, Verification and Modelling who are building the next generation chipset APO for L1 - closely collaborating with LPOs of FPGA Design, FXP Design, Verification & Emulation, L1 SW, L1 Integration teams that ensure delivery of 5G features for Test UE 5G Test UE Development in Stratix10 FPGA.LPO for L1 - FPGA Design, FXP Design, Verification & Emulation

  • Squad Group Manager

    Apr 2023 - now

  • Squad Group Leader, SoC

    Mar 2022 - Apr 2023

  • Area Product Owner - L1

    Mar 2020 - Mar 2022

  • FPGA Architect, Local Product Owner

    Jan 2019 - Feb 2020