Deep Enrich
Pullepu Jaswanth
Intern
2000 followers
Bengaluru, Karnataka, India
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About me
Physical Design Engineer at Leadsoc Technologies private limited | VLSI Design
Education
Mahati English Medium school
-SSCSMVM Polytechnic college,Tanuku
2012 - 2015Diploma Electronics and Communication Engineering.webp)
Sasi Institute of Technology & Engineering, Kadakatla, Tadepalligudem, Pin-534101(CC-K6)
2015 - 2018B.Tech Electronics and Communication Engineering
Jawaharlal Nehru Technological University
2018 - 2021M.Tech Digital electronics and communication systems 8.5
Experience
Entuple Technologies Pvt. Ltd.
May 2019 - Jun 2019InternKnown About the Cadence tools usage and had hands on experience of analog layout and design
SION Semiconductors Private Limited
Oct 2019 - Apr 2020Intern
SignOff Semiconductors
Dec 2021 - Mar 2024Design Engineer - IWorked for AMD odc for Technology node 5nm,6nmInhouse project For technology node 16nm
LeadSoc Technologies Pvt Ltd
Mar 2024 - nowPhysical Design EngineerClient - Mediatek
Licenses & Certifications
CMOS Digital VLSI design
NPTELApr 2019- View certificate
IC Compiler II: Block Level Implementation Exam
Synopsys IncMar 2023
- View certificate
VSD - Static Timing Analysis - II
UdemyMay 2021 - View certificate
VSD-Static Timing Analysis-I
UdemyMar 2021 
VLSI design methodologies
Maven SiliconJan 2019- View certificate
VSD-Physical Design Flow
UdemyMar 2021 - View certificate
Cadence RTL-to-GDSII Flow v4.0 Exam
Cadence Design SystemsJan 2023 - View certificate
Competitive Programming with Python
REGex Software ServicesAug 2021 
Physical Design and Verification
Entuple Technologies Pvt. Ltd.Jul 2021
Languages
- enEnglish
- hiHindi
- teTelugu
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