Experience

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  Stmicroelectronics

  Mar 1995 - Oct 1997

  Design engineer

  ▪ Synthesis and DFT of a Sigma-Delta A/D and D/A converter and Video CODEC.▪ Verification and automation of standard cell library front-end models

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  Philips semiconductors

  Nov 1997 - Jan 2001

  Design engineer

  ▪ Design of a full speed USB device and a standalone USB hub

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  Mahi networks

  Jan 2001 - Oct 2002

  Member technical staff

  ▪ Responsible for verification of networking IPs like protocol-to-protocol bridge, buffer manager, scheduler and switch interfaces using advanced verification language.

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  0-in design automation [mentor graphics]

  Oct 2002 - May 2004

  Design verification consultant

  ▪ Responsible for working with the R&D and sales team to enable external customers deploy complex assertion based formal and dynamic simulation tools and methodologies to find corner case design bugs.▪ A proven track record of multiple customer wins by demonstrating creative problem-solving techniques using 0-In formal verification tools suite.

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  Intel corporation

  Jun 2004 - Sept 2024

  ▪ A senior leader accountable to deliver a portfolio of IO SIPs to Intel server and client products. The IP portfolio comprises of a diverse set of IPs ranging from Virtualization, CXL, PCIe, Host IO bridge, UCIe, Accelerators and a complex IO logical Phy. Proven track record in delivering high quality IO SIPs to multiple generations of server and client products.▪ Managing a highly talented and diverse team of approximately 300 IP design engineers across USA, India and Malaysia design centers. Successfully turned around the quality of IP deliverables by driving IP transformation initiatives.▪ Responsible to define the IP roadmap for server IO technologies with close collaboration with product and business unit teams Show less

  • Senior Director

    Apr 2020 - Sept 2024

  • Engineering Manager

    Jun 2004 - Mar 2020
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  Amd

  Sept 2024 - now

  Senior director of server systems engineering