Karan Gohil

Experience

• 

  Maxim Integrated

  Mar 2017 - Jul 2021

  • Single point of contact for identifying, investigating, and driving resolution of the systematic yield limiting problems at inline defect for Tower Semiconductor foundry• Ownership of one of the HVM 180 nm automotive technologies (200 mm) for electrical test Cpk Improvement• Disposition of holds at electrical test with cycle time and quality improvement• Root cause analysis and assignment of RTV wafer scraps at electrical test • Defect source analysis, tool commonality and regular excursion reporting to local and global teams• Statistical process chart(SPC) set up for Inline production monitoring• Continuous monitoring and improvement of OOC trends for Inline SPC and Parametric test• Root cause analysis of low yield products at final test•Defect Data analysis and reporting using KLA-KLARITY ACE Yield Correlation and Analysis Software

  • Yield Engineer II

    Sept 2020 - Jul 2021

  • Yield Engineer I

    Mar 2017 - Sept 2020
• 

  ON Semiconductor

  Jul 2021 - now

  Senior Product Engineer

  • Focused on the development and release of new product technologies from initial silicon to mass production for the image sensing and automotive markets• Ownership of wafer and package level validation of CMOS image sensors on bench as well as probe station • Debug initial silicon and validate design features• Determine root cause of problems (process, test, or design-related)• Participate in yield analysis, generate & drive necessary debug actions to improve yield