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Amit Kr. Garg

Amit Kr. Garg

Faculty in ECE

Followers of Amit Kr. Garg2000 followers
location of Amit Kr. GargNoida, Uttar Pradesh, India

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  • Timeline

  • About me

    SoC Power || EM || IR || 3DIC || Thermal

  • Education

    • Kurukshetra University

      1995 - 1999
      Bachelor of Technology (B.Tech.) Electrical, Electronics and Communications Engineering First

      B.Tech (ECE) from M.M. Engineering College, Ambala (KUK). 1999

    • Panjab University

      2002 - 2004
      Master of Technology (M.Tech.) Microelectronics (VLSI)

      • M.Tech (Microelectronics) from UCIM, Panjab University, Chandigarh. 2004

  • Experience

    • JIET, JIND

      Sept 2000 - Jun 2002
      Faculty in ECE

    • Semiconductor laboratory, Mohali

      May 2004 - Feb 2008
      Scientist- SC

      • Responsible for to work on Front-end and Back-end Design flows for Digital ASICs.• Customized digital library development• Physical design (Custom layout of standard Cells, Floor-plan, Placement and Routing). • Post layout Verifications

    • Cadence Design Systems

      Mar 2008 - Sept 2023

      • Own Foundry Certifications for Cadence Design System, Inc. backend sign-off products for EMIR.• Responsible for quality signoff and release of Transistor Level & full-chip EMIR analysis EDA Tools: Voltus-Fi, Voltus & Spectre-EMIR solutions.•Worked on multiple customer projects like Apple, ST, Freescale, TI, Broadcom & TSMC.

      • Product Engineering Director

        Jan 2023 - Sept 2023

      • Sr. Product Engineering Manager

        Jul 2017 - Jan 2023

      • Principal Product Engineer

        Jul 2014 - Jun 2017

      • Lead Product Engineer

        Mar 2008 - Jun 2014

    • Microsoft

      Sept 2023 - now
      Principal Silicon Power Integrity CAD Manager

      I am responsible for development and CAD automation for power integrity sign-off methodologies for Microsoft-IDC's silicon physical design groups.

  • Licenses & Certifications