
Manish Tiwari
FPGA Design Intern

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About me
Senior Verification Engineer at Microsoft
Education

Govind Ballabh Pant Krishi Evam Praudyogik Vishwavidyalaya
2005 - 2009Bachelor's Degree Electrical Engineering 8.293/10Activities and Societies: Engineering Society, Pantnagar 1. Awarded with Best outgoing Electrical Engineering Student Scholarship in batch 2005-09.

Georgia Institute of Technology
2020 - 2023Master of Science - MS Computer ScienceMaster's in computer science with focus on Machine Learning & Artificial Intelligence Coursework:Machine LearningReinforcement LearningDeep LearningAI for RoboticsMachine Learning for TradingComputer VisionAI EthicsComputer Algorithms Software Architecture DesignSoftware Development Process

North Carolina State University
2014 - 2016Master's Degree Computer Engineering 3.66/4.0Graduate degree in Computer Engineering with an area of emphasis for the Digital design, Verification and test and computer architecture For more information about the course work please visit:http://www.ece.ncsu.edu/research/cas
Experience

Indian Institute of Technology, Roorkee
May 2008 - Jul 2009FPGA Design InternDevelopment of “Digital Electronics Lab Experiments module on Single FPGA Chip “ Design of a multicomponent FPGA based system to facilitate students understand and perform the basic experiments of Digital Logic course.Modeling and simulation of basic sequential and combinational components using VHDL and XILINX compiler and synthesis on SPARTAN KIT.

Maruti Suzuki India Limited
Aug 2009 - Aug 2011Assistant Manager - Electrical Control
Cummins Inc.
Aug 2011 - Jul 2014Manager
Tesla Motors
May 2015 - Aug 2015Intern
IEEE
Jan 2016 - Mar 2018Communication Committee Chair-Eastern North Carolina Section
Analog Devices
Feb 2016 - Oct 2021Design Verification Engineer• Worked on Design Verification of some of the most complex and advanced digital 4G/5Gtransceiver SOCs.• Developed block and chip-level functional verificationstrategies and plan based on design requirements and system architecture.• Developed modular and configurable UVM based test bench environments for directed,constrained random tests for signal manipulation modules in data pipeline for digital 5Greceiver.• Implemented Coverage driven verification methodologies and formulated functionalcoverage metrics.• Hands-on experience in performing gate-level verification on netlists with SDF backannotated simulations using Cadence Xcelium ecosystem tools.• Coordinated with Physical Design and STA teams to ensure the timing closure progressionsare in line with the Gate Level Simulation expectations while meeting the project objectives.• Experienced in every phase of the design from the pre-silicon stage of design-for-testabilityverification to the post-silicon stage of ATE testing and debug.• Performed Scan pattern generation for Stuck-at and at-speed transition delay faults andelaborate test coverage analysis with Cadence Modus tools Show less

Microsoft
Oct 2021 - nowSenior Design Verification Engineer
Licenses & Certifications

Six Sigma Green Belt
Cummins Inc.Jun 2014
TS 16949 Internal Auditor
Maruti Suzuki India LimitedNov 2010- View certificate

Microsoft Global Hackathon Executive Challenge 2023 Honorable Mention
MicrosoftNov 2023 - View certificate

Microsoft Global Hackathon 2025 Award Winner
MicrosoftNov 2025 - View certificate

Microsoft Global Hackathon 2022 Award Winner - Local Venue (Raleigh)
MicrosoftDec 2022 - View certificate

Microsoft Global Hackathon 2023 Award Winner
MicrosoftNov 2023 - View certificate

Microsoft Global Hackathon 2024 Executive Challenge Winner
MicrosoftNov 2024
Honors & Awards
- Awarded to Manish TiwariBest Employee in the Q1 2012 Plant Leadership Team Mar 2012
- Awarded to Manish TiwariBest Student- Electrical Engineering, 2009 Govind Ballabh Pant Krishi Evam Praudyogik Vishwavidyalaya May 2009
Volunteer Experience
Project Member, Blood Donation Drive
Issued by Cummins Inc. on Oct 2013
Associated with Manish Tiwari
Languages
- enEnglish
- hiHindi
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