Jason Yuchi Tsao

Experience

• 

  ProMOS Technologies

  May 2003 - Jun 2005

  Wafer Sort Engineer

  • Fabrication of DRAM products; wafer data test and trouble shooting.• Cooperating with QA team for wafer yield analysis and enhancement.

• 

  Illinois Institute of Technology

  Sept 2007 - Nov 2011

  • Area-efficient VLSI implementation for parallel linear-phase digital FIR filter of even and odd length.• Cost reduction for high-speed pipeline IDCT/DCT VLSI architectures based on time rescaling.• Cost-Reduced high-speed VLSI architectures for lattice digital filters based on cut-set localization. • Power reduction for VLSI pipeline system (Multimedia mobile processors) by means of single comparator-based clock gating. • ECE212: Circuit Analysis• ECE429: Introduction to VLSI Design

  • Research Assistant

    Sept 2007 - Nov 2011

  • Teaching Assistant

    Sept 2007 - May 2011
• 

  Qualcomm

  Aug 2012 - Aug 2018

  ASIC Implementation Engineer

  • Participating ASIC implementation of GPU cores• Physical Aware Synthesis (DCG) and Timing closure (STA) before handoff to PD• Formal Verification• Static Timing Analysis (STA)• Floorplan deployment for large blocks up to 5.1 millions of gates • Conformal LEC/Formality for each stage of Synthesis and ECO, from RTL to PD netlist• FV in line with Synthesis and ECO, and create constraints for MBIST/DFT• Debugging Non-Equivalence (NEQ) and resolving Aborts• Automation of FV flow Show less

• 

  EpicPoint Properties

  Jan 2020 - Jan 2021

  Realtor®

  Quality service with competitive rebates.Satisfaction Guaranteed.DRE #02121838

• 

  Qualcomm

  Feb 2021 - May 2022

  EngIT Engineer
• 

  Intel Corporation

  Aug 2022 - now

  Software Engineer