Deep Enrich
Prananya Reddy M
Design & Verification Intern
9000 followers
Bengaluru, Karnataka, India
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About me
Application Engineer at Siemens EDA
Education
New Baldwin International PU College
2016 - 2018Class 12 PCMB 87%New Baldwin International School
2015 - 2016Class 10 CBSE 10CGPA
Visvesvaraya Technological University
2019 - 2023Bachelor of Engineering - BE Electronics and Communications Engineering 8.3
Experience
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Defence Research and Development Organisation (DRDO)
Mar 2022 - Nov 2022Design & Verification Intern•Developed Application code for various interfaces and applications. Designing the Testing Methodology.•Worked on Verifying Communication Protocols(UART,SPI).•Wrote, Debugged Various Testbench.
Alphawave Semi
Jan 2023 - Jun 2023Application Engineering Intern•Worked on QA checks and Customer releases for QSPI IP.
Cadence Design Systems
Jul 2023 - Jun 2024Design Engineering Intern• Formal Verification.• Tool: Jasper gold.• System Verilog Assertions.• Formal Verification of a block in PCIe DLL.
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Siemens EDA (Siemens Digital Industries Software)
Jul 2024 - nowApplication EngineerFormal Application Engineer
Licenses & Certifications
VLSI Soc Design using Verilog HDL
Maven SiliconDec 2022
Digital Systems: From Logic Gates to Processors
Universitat Autònoma de BarcelonaOct 2022- View certificate
Learning Verilog for FPGA Development
LinkedInNov 2022
- View certificate
Hello FPGA
Microchip Technology Inc.Oct 2022 - View certificate
PYTHON
UdemyJan 2022 VLSI System On Chip Design
Maven SiliconMar 2023- View certificate
Learning FPGA Development
LinkedInDec 2022 - View certificate
Debugging Techniques for Serial Communications (I2C/SPI/UART)
Microchip Technology Inc.Nov 2022 - View certificate
Practical I2C: Introduction, Implementation and Troubleshooting
Microchip Technology Inc.Nov 2022 - View certificate
The Fundamentals of Digital Marketing
GoogleApr 2022
Languages
- enEnglish
- kaKannada
- teTelugu
- taTamil
- hiHindi
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