Experience

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  Tsmc

  Jul 2002 - Sept 2006

  Senior process integration engineer

  07/2004 - 09/2006, Senior Process Integration Engineer- Responsible for 0.25um embedded flash memory product line and report to the customer, Freescale. The products are automobile parts with the highest reliability and quality requirement. Bi-weekly host regular meetings with the customer and the manufacturing end.- Detect any abnormal event according to the wafer acceptance test (WAT) and find the cause.- Response to customers’ request of process change, such as ED matrix exam and implant dosage fine-tunes.- Collaborate with customers and product engineers to improve yield continuously. - Develop and maintain quality system. Included FMEA update, SPC review and nonconforming wafers control. - Coordinated customer and internal audit. Successfully help TSMC Fab3 earned ISO/UL certification in 2005 and 2006. Won Quality Expert Award in 2005. 07/2002 - 07/2004, Defect Reduction Engineer- Identify the possible sources of wafer defects and request the responsible departments for improvement; in more complicated cases, conduct various experiments to rule out or narrow down the targets. - Initiate defect reduction proposals and coordinate process and equipment departments to test and deliver the results. - Through characteristic and logical approaches, successfully solved a complicated wafer damage case, 150 wafers were susceptible to be impacted each week in 2004. - Honored with the Most Favorite Engineer title in the process integration department in 2003. Show less

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  University of texas at austin

  Jan 2008 - Dec 2009

  Teaching assistant

  9/2009 – 1/2010, Teaching Assistant - Electronic Circuit-1 Lab- Instruct sophomore and junior students on the fundamental circuit concepts and theories. Exercise the testing practices on various devices to demonstrate the characteristics shown in circuit theory textbooks. - Evaluate the quality of work and effort of the students in the class. Conduct a comprehensive interview with each student in the final exam to assess the acquaintance of their circuit knowledge learned in the lab. -The labs included simulation and building of diodes rectifier, BJT/MOS I-V curve and amplifier. 9/2008 – 1/2009: Teaching Assistant - Mixed Signal and Circuit Lab- Design curriculum for junior and senior students and pretest/pre-run the circuit modules. Coding with Spices and Labview to simulate and retrieve the test results. - Challenge student in design logic and circuit performance and conduct face to face final exam. -The labs included simulation and building of DAC, ADC, filters and delta-sigma modulation. Show less

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  Amd

  Jun 2012 - Dec 2012

  Senior product develope engineer

  - Responsible for 28nm thermal IP for GPU in game console. The goal is to make diodes report correct temperature through ADC. Focus on the calibration method and the test plan, determine the fuse values of all related variables, and develop ATE test program.

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  Applied optoelectronics, inc.

  Jan 2013 - Jan 2022

  Senior quality and process integration engineer

  - Responsible for the quality of edge emitting DFB and FP laser chips. Major final products are 40G and 100G transceivers- Correlate testing and reliability data to process steps to improve yield or solve problems. Cooperate with testing, dicing and packaging department to improve manufacturability. - Responsible for quality management system in semiconductor product department, including engineering change, process capability monitor, failure analysis for RMA, inspection and nonconforming product management.- Reliability testing and analysis. Using ILX-9434 to perform acceleration aging test. Develop Labview program to manage testing data and using JMP for statistical analysis. Develop chip aging model.- Customer technical support. Coordinate customer audit. Answer customer’s questions about reliability and new product implement. Show less

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  Ii-vi incorporated

  Feb 2022 - now

  Process integration engineer