Trevis Lunsford

Experience

• 

  NCR

  Mar 1970 - Feb 1983

  Engineer

  Some responsibilities were to write 8051 assembler code for magnetic stripe readers and to contribute to design and testing of cash registers. Assisted with EMI/RFI testing of cash registers and incorporation of resultant design modifications.

• 

  BancTec

  Feb 1983 - Oct 2000

  Principal Engineer

  Responsibilities were to design electronic hardware utilizing microprocessors, memories, TTL & CMOS logic chips, FPGAs and CPLDs. These designs were for a myriad of purposes including optical character recognition, ink jets, E13B printer stepper motor control and microfilming. Tool usage included OrCad for shematic capture, PADS for PCB artwork, 8085 & 8051 assemblers and C compilers, Xilinx ISE along with Palasm type tools.

• 

  Metera Networks

  Jan 2000 - Jan 2001

  ASIC Engineer

  Some responsibilities were: Contribute to writing detailed chip architecture and specification documents using Frame Maker. Write RTL code in Verilog to implement the specifications into the FPGA. Simulate and verify the FPGA using NCSim.

• 

  Cicada Semiconductor

  Oct 2001 - Mar 2002

  Applications Engineer

  My responsibility was to design FPGA logic to be used on a development board for the express purpose of testing an ASIC designed by other team members.

• 

  Ceterus Networks

  Mar 2002 - Dec 2008

  Senior FPGA Design Engineer

  My responsibilities were to design Xilinx or Altera FPGA and CPLD logic to run on proprietary hardware for the telecommunications industry. I also wrote testbenches and testcases to simulate and verify the designs. Participated in lab testing the products with bench testers, oscilloscopes, logic analyzers and Xilinx ChipScope and Altera SignalTap.

• 

  ADVA Optical Networking

  Jan 2009 - Jun 2010

  FPGA Engineer

  My responsibilities were designing module testbenches and testcases and contributing to full chip tests as well using System Verilog and UVM verification.

• 

  Overture Networks

  Jul 2010 - Nov 2012

  Senior Engineer II - FPGA

  My responsibilities were designing RTL code to implement Ethernet and SONET/LCAS protocols in FPGAs and designing bus functional models, testbenches and testcases to simulate and verify FPGA designs. Verilog and System Verilog was mostly used along with some UVM and also some VHDL.

• 

  Mustang Technology

  Mar 2013 - May 2013

  Contract FPGA Engineer

  Designed FPGA logic implemented on COTS eval/demo boards for radar related DoD proof of concept. Obtained security clearance. Resigned after the sale of our Texas house in order to return to Charlotte after 18 years in DFW.

• 

  Aramark Healthcare Technologies

  Aug 2013 - Dec 2014

  Senior Electronics Engineer

  Responsibilities included researching design details of OEM medical imaging diagnostic equipment to discover the faulty components and develop repair & test procedures. Some of these circuits were centered on FPGAs, CPLDs, DSPs, CPUs and memory.