Experience

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  Accenture

  Jul 2010 - Dec 2012

  Software engineer

  Software Engineer • Improved the productivity of modules using COBOL and JCL. • Developed essential intellectual business logic in the form of business rules. • Carried out Impact analysis, to identify the potential consequences of a change in a module/portfolio.

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  Max planck institute for physics

  Sept 2014 - Mar 2015

  Intern

  Laser Interferometer for Gravitational Wave Observatory (LIGO) • Built a highly reflective mirror suspensions for studying the quantum radiation pressure noise. • The mirror movement in X, Y, Z, Pitch, Roll and Yaw are controlled using coil magnet actuators. • A powerful laser is shot on to the mirror to study the effects of quantum radiation pressure noise. • The build suspension is evaluated, analysed, and characterized as per the requirements.

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  Jiva sciences pvt. ltd.

  Mar 2016 - Aug 2018

  Firmware engineer

  Firmware Development • Designed and developed RTL logic for real-time cell sorting in microfluidic systems. • Developed novel algorithms to analyse real-time sensor data on ARM processor. • Led a team of interns to deploy the module at the client location.

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  National cheng kung university

  Sept 2018 - Jul 2023

  Research scholar

  Fe-SRAM • Designed variation-tolerant Fe-SRAM cells for ultra-low power edge computing applications. • Fe-SRAM eliminates static leakage current yielding a break-even time of 4.2 ms. • Developed and calibrated a novel Verilog-A compact model for Fe-capacitors. • Taped out SRAM chip for memory and compute-in-memory applications using TSMC TN40G node. • Analysed the impact of ferroelectric scaling on SRAM stability, latency and power. Fe-FinFET • Characterized Ferroelectric- FinFET and modelled the reliability of the device. • The reliability model is used to study the impact on neural network built using Fe-FinFETs.CIMulator • Characterized, modelled, optimized and benchmarked non-volatile memories such as RRAM, PCM, FeRAM, SRAM. • Characterized lab made CFET device, proposed novel architecture resulting in performance improvement of 10 to 15-fold in TOPS per watt per unit area. Show less

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  Imec

  Jul 2023 - now

  Postdoctoral researcher

  1-bit/Multi-bit Domain-wall Memory • Proposed several 1-bit/multi-bit domain wall memory cell configurations. • Developed behavioural model of domain wall motion. • Optimized the performance of the memory bitcells. • Developed and modelled innovative hardware architectures for multi-bit domain wall memory. • Innovated data pipelining and parallelism methods to support high bandwidth read/write access. • Benchmarked the memory cell configurations against various memory configurations. Show less