Armando Biscontini

Experience

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  Skyward Experimental Rocketry

  Jun 2012 - Oct 2014

  Led the team responsible for the development of the electronic systems of Rocksanne I-X, first sounding rocket of the Rocksanne Program. The systems’ tasks were: (i) ignition of the solid rocket engine; (ii) logging and storage of physical quantities gathered from on-board sensors (accelerations, rotations, atmospheric pressures, temperatures) in order to estimate state and attitude of the aircraft; (iii) communications and geolocation; (iv) smart activation of deceleration and main parachutes. The rocket completed a total of 3 launch campaigns with no electrical failures and all the systems performing as expected. Show less

  • Head of Electronics Department

    Oct 2012 - Oct 2014

  • Integrated Project Team Leader - Electronic Systems Team

    Jun 2012 - Jun 2014
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  Center of Micronanotechnology - EPFL

  Mar 2015 - Aug 2015

  Cleanroom researcher

  Designed and fabricated in cleanroom a RRAM array of 96 memory cells using Pt/HfO2/Ti/Pt technology. The process flow involved lithography, deposition (sputtering and ALD) and dry etching steps in order to define memory elements with 25 sq μm effective area (1 μm feature size).

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  Utah Nanofab

  Feb 2016 - Aug 2016

  Cleanroom researcher

  Contributed to the development of a process flow for the microfabrication of RRAM arrays with Pt/HfO2/TiO2/Pt technology.

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  University of Utah - Employment

  Feb 2016 - Aug 2016

  Researcher

  Carried out research in the resistive memories field with a focus on RRAM technology co-integration in the Back End of Line (BEoL) of 180nm CMOS process. In order to support the design of RRAM elements for ordinary cleanroom processes, Calibre and Cadence design-kits (DRC and LVS) have been successfully developed and tested.

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  Qualcomm

  Apr 2017 - now

  Research interests:• Machine Learning applications to Electronic Design Automation• Optimization of silicon design methodology Engaged in the VLSI back-end methodology and EDA research aimed to optimize the design process and technology of latest silicon nodes. Involved in the physical design development of high-speed telecommunication modules for premium tier System-on-Chip platforms.

  • Staff Engineer

    Dec 2022 - now

  • Senior Engineer

    Nov 2018 - Dec 2022

  • Engineer

    Apr 2017 - Nov 2018