Chaitanya Kakade

Chaitanya Kakade

Junior Engineer

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  • Timeline

  • About me

    ASIC Physiacal Design And Verification Engineer Trainee at Entuple Technologies Pvt. Ltd.

  • Education

    • AISSMS Institute of Information Technology

      2015 - 2019
      Bachelor of Engineering Electronics And Telecommunication Engineering A

      Activities and Societies: Participate in technical programs, Poster presentation,Quiz compitition, Sports, Cultural activities, NSS activities, Member of IETE Society. Successfully completed a graduation in Electronics and Telecommunication Engineering. In those 4 years I've learnt more things. the knowledge that I gained helps my future journey. Being an engineer I've participated in extra curricular activities. Attend webinar, programs, workshops relevant to the engineering.

    • Vishwakarma Institute Of Technology

      2013 - 2015
      Higher Secondory Certificate Examination A
    • Deccan Education Society

      2007 - 2013
      Secondary School Certificate Examination A
  • Experience

    • Bharat Electronics Limited

      Dec 2019 - Dec 2020
      Junior Engineer

      I've worked in the Electro-Optics department under that electronics testing section I have done assembly of electronics components on the PCB, PCB testing, Overcome Troubleshoot in that PCB designing. Environmental testing of the final unit. Final testing of the product.

    • Varroc

      Apr 2022 - Dec 2022
      Quality Assurance Engineer

      In Quality Assurance I've worked in the IQA (Inward Quality Assurance) department. In that I've worked with SAP (System Application Product). I know the quality and material management transaction, testing the quality of electronics components and checking with the analog and digital instruments, Check the PCB board with the PCB design. Make the PIR (Part Inspection Report), SIR (Sample Inspection Report) & AOI (Aggregate Of Inspection). Follow the Kaizen rule and Pokayoke. Maintain 5s throughout the process. Show less

    • Entuple Technologies Pvt. Ltd.

      Jul 2023 - now
      Physiacal Design Engineer Trainee

      I am exploring the concepts of VLSI.

  • Licenses & Certifications

    • Innovus Hierarchical Implementation with Stylus Common UI v22.1 Exam

      Cadence Design Systems
      Dec 2023
      View certificate certificate
    • Cadence RTL-to-GDSII Flow v5.0 Exam

      Cadence Design Systems
      Nov 2023
      View certificate certificate
    • Genus Synthesis Solution with Stylus Common UI v22.1 Exam

      Cadence Design Systems
      Jan 2024
      View certificate certificate
    • Cadence and Entuple: Digital Physical Design

      Cadence Design Systems
      Jan 2024
      View certificate certificate
    • Innovus Block Implementation with Stylus Common UI v22.1

      Cadence Design Systems
      Dec 2023
      View certificate certificate
    • Basic Static Timing Analysis v3.0 Exam

      Cadence Design Systems
      Dec 2023
      View certificate certificate