Rajesh Vivekanandham

Experience

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  Oracle

  Jan 2003 - Jan 2003

  Applications Engineer

  Worked with Oracle Student Systems Enrollments module team. I had fun optimizing some ridiculously long (3-4 printed pages) and complex sql queries.

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  Advanced Micro Devices

  Jan 2005 - Jan 2010

  Sr. Design Engineer

  I was with the performance team developing and utilizing cycle accurate simulators to dream up/evaluate micro-architectural features for the hound and bobcat family of cores at AMD Bangalore. I also worked extensively on client workload characterization and tracing. I was a part of the ~15 strong arch/perf/rtl/val/ckt team that was involved in proposing and pushing for Llano APU to be the first part on the AMD Fusion road-map. I helped build and evaluate a couple of performance and power mgmt features on the Llano core and contributed to functional validation of the new hw int srt divider. I also brought up the AMD Bangalore client x86 performance lab and worked on competitive performance measurements, analysis and projections. Towards the end of my stint there, I worked on the L2 unit of Jaguar, the SoC in the Sony PS4 and Xbox One Show less

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  Intel India Technology Pvt Ltd

  Jan 2010 - Jan 2022

  Principal Engineer

  I was initially with the team building and using cycle accurate simulators to dream up/evaluate micro-architectural features for the Xeon server SoCs at Intel India. I was a part of the ~10 member team that put Xeon D on the Intel roadmap. I was lucky enough to contribute to the chip, system and rack level perf/watt/$ analysis and trade offs for the proposal. I then continued to work on it towards pre and post si performance up to the launch. Of this product, Anandtech said "Xeon D is probably the most awesome product Intel has delivered in years" . https://www.anandtech.com/show/9185/intel-xeon-d-review-performance-per-watt-server-soc-champion/ . After this, i helped with a follow up product , Xeon D NS, through the entire cycle (put on roadmap, execute, validate) again.I then had a brief stint working for an intrapreneurial group at PSG (Altera@Intel). Here i was among the first to identify the value prop of tight on platform integration of Xeons and FPGAs using UPI and enumerating the reasons why it would have the best attributes of 2 worlds, both Xeon FPGA MCPs and discrete PCIe FPGA solutions. https://www.anandtech.com/show/14906/intel-ships-stratix-10-dx . I also helped with a prior version of the Stratix 10 optimized for Deep learning https://www.intel.com/content/www/us/en/products/programmable/fpga/stratix-10/nx.htmlSubsequently, i worked on SoC performance and workload characterization with a focus on deep learning and other gpgpu workloads for the Xe line of datacenter discrete gpus announced recently (Xe HP and HPC) . I worked towards an aggressive large last level cache, high bw Xe links and balancing HBM bw needs on Ponte Vecchio.Towards the end of my stint at Intel India, i helped explore new programmable architectures in the data center products group. Show less

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  AMD

  Jan 2022 - Jan 2024

  Performance Engineer

  I was a performance engineer with a focus on server solutions at the data center business unit. This included a focus on custom parts for large cloud customers, working directly with large hyperscalers in China and inference workloads on CPUs,

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  Agrani Labs

  Jan 2024 - now

  Co-Founder

  We are currently in stealth mode.