Hunter Shi

Hunter Shi

IBM Power5/5+ Equipment Engineer

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  • Timeline

  • About me

    Senior Engineer for Z17 mainframe Telnum II manufacturing lead

  • Education

    • SUNY New Paltz

      2000 - 2005
      Bachelor of Engineering (B.E.) Control System A

      Activities and Societies: -2004 SUNY Chancellor Award Recipient -Vice President IEEE -President of Eta Kappa Nu -Who is Who Dean's list.

  • Experience

    • IBM Power Systems

      Jul 2004 - Oct 2007
      IBM Power5/5+ Equipment Engineer

      Trained 4 shift of equipment maintenance team on keeping 300+ Tester available for all time.Program and update the Tester control system with PLC language

    • IBM Power Systems

      May 2009 - Dec 2011
      Functional Engineer for IBM Power 775 PERCS modules

      Functional Engineer for IBM IOHUB fiber optic 3D module, Quad-Chip Power 7 Module, and IOHUB chip on wafer and module characterization.-Program SAS code to do auto-cron reports-Created the file and data structure for generate fiber optic data and report structure, which assisted the manufacturing on delivering the defect free 3D modules (with fiber optic cables attached)

    • IBM z Systems

      Jan 2012 - Aug 2024

      Characterization on Z14 & ZR1 mainframe chip on defect, yield, functional and power performance learning. Overall Mainframe processor and Cache chips' Yield, Defect, Functional and Power Performance characterization on wafer and module level. processor and cache chip wafer and module characterization on defect, yield,functional and power performance.Received Corporate Award on zEC12 delivery.

      • Senior Engineer for Z16 mainframe Telnum Processor's wafer & module Characterization.

        Aug 2020 - Aug 2024
      • Senior Engineer for Z15 mainframe CP and IO cache chips' wafer & module Characterization.

        Aug 2018 - Dec 2020
      • Senior Engineer on Z14 and ZR1 Mainframe Processor and Cache Chips Characterization

        Aug 2016 - Jul 2019
      • Functional Characterization Engineer for Z13 and Z13s processor and cache chip

        Feb 2014 - Aug 2016
      • Characterization Engineer for zEC12 mainframe processor chip and module

        Jan 2012 - Feb 2014
    • IBM

      Jan 2023 - now

      Lead the overall hardware delivery, planning and data analysis from early user hardware to production. yield and characterization on Telum II processor on wafer and module, lead manufacturing engineer on hardware movement and manufacturing process

      • Lead Senior Manufacturing Engineer on IBM Spyre AI chip

        Oct 2024 - now
      • Senior Engineer for Z17 mainframe Telnum II Processor Manufacturing lead.

        Jan 2023 - now
  • Licenses & Certifications