Sazadur Rahman, Ph.D.

Experience

• 

  PrimeSilicon technology Inc

  Sept 2014 - Mar 2017

  1. Taped out a 28nm tech node 22x17.3 mm2 chip of 140M gate count using- AtopTech Aprisa, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Calibre Physical Verification, Conformal LEC.2. Taped out a 28nm tech node 11x11 mm2 chip of 57M gate count using- Innovus Implementation system, Synopsys PrimeTime Suite, starRC, Formality, Calibre Physical Verification, Voltus IC.3. Taped out a 14nm tech node 12x13 mm2 chip using- AtopTech Aprisa, Synopsys IC Compiler II, PrimeTime Suite, starRC, Formality, Calibre Physical Verification, Voltus IC. Show less

  • Senior ASIC Physical Design Engineer (Team Leader)

    Feb 2017 - Mar 2017

  • ASIC Physical Design Engineer

    Sept 2014 - Jan 2017
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  Neural Semiconductor, DBL Group

  Apr 2017 - Dec 2017

  Senior Design Engineer

  As a startup VLSI design center in Bangladesh we are currently building team, running training sessions for fresh Design Engineers to expose our-self as a world class ASIC logic and physical design center.

• 

  ECE, University of Florida

  Jan 2018 - Dec 2022

  Graduate Research Assistant

  Research Assistant at FICS (Florida Institute of Cyber Security) Research,Department of ECE, University of Florida

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  Intel Corporation

  Jan 2020 - May 2020

  Hardware Security Intern

  3DXP hardware verification for FIPS 140-3 certification -1. Perform the NIST Cryptographic Algo. Verification Program (CAVP) on Intel crypto engines using CST laboratory vectors2. Develop firmware for official FIPS 140-3 certificate testing and data collection

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  Intel Corporation

  May 2021 - Aug 2021

  Security Researcher

  Threat Model Database development for Security Architecture Engineering (SAE) Group / IPAS1. Developed threat models for different adversary models based on their capabilities, e.g., SW, side-channel, bios, physical, etc.2. Helped developing an automated threat model review (TMR) tool to expedite the security analysis for security architects.

• 

  Intel Corporation

  Jan 2023 - Aug 2023

  Security Assurance Architecture Engineer

  Worked in the Product Architecture Response and Remediation team as a Silicon Security Architect and threat modeling expert.

• 

  UCF Electrical and Computer Engineering

  Aug 2023 - now

  Assistant Professor

  Sazadur is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at University of Central Florida. He is affiliated with both ECE and CS department at UCF under the “Cyber Security and Privacy Cluster”.