Chad Coburn

Experience

• 

  NXP acquires Freescale Semiconductor

  Jul 2004 - Jun 2007

  For my first year of employment with Freescale, I participated in the Engineering Rotation Program where every 3 months I chose an aspect of engineering to explore within the company. Rotation 1: Design verification of the completion block for a Power Architecture core in the networking and computing systems advanced technology division (e700 core). Rotation 2: Logic design of a test control block in the wireless and mobile systems group.Rotation 3: Performance analysis of different process technologies for a circuit design team in the libraries and memories group.Rotation 4: Logic design of a test-mode system interface block for a Power Architecture core. At the end of this rotation, I stayed on as a final placement in the e500 core logic design team. Show less

  • Logic Design Engineer

    Aug 2005 - Jun 2007

  • Engineering Rotation Program Participant

    Jul 2004 - Aug 2005
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  IT Freedom

  Oct 2007 - Jun 2008

  Network Tech. / Purchasing Manager

  Provided remote and on-site technical support to 15+ small-to-medium sized businesses.Managed purchasing computer and VoIP software and hardware needs of our company and the businesses we supported.

• 

  Intel Corporation

  Jul 2008 - now

  Technical lead and manager responsible for IP RTL development, SoC RTL integration, and overall front-end delivery, execution, and program management of a gigabit Ethernet switch used in 5G server networking SOCs. Technical lead responsible for RTL integration and front-end delivery of DDR memory and scalable coherent fabric interconnect subsystems into 5G server networking SOCs. RTL / ASIC logic design and verification engineer focusing on development of next-generation (LTE and 5G/NR) wireless modems. RTL / ASIC logic design and validation of network traffic management IP for mobile base-station products. Verification of CPU power management features for server products. Power architect responsible for usecase power consumption estimation, optimization and modeling of XMM7560 Baseband LTE modem and mobile application processor SOC platforms. RTL / ASIC Logic design of next-generation mobile SOCs for smartphones and tablets.Expertise in 2-D Display Controller micro-architecture and design.- Responsible for micro-architecture specification and implementation, IP development and IP integration (internal Hard IPs and 3rd-party external IP).

  • Principal Engineer, SoC Logic Design

    Apr 2024 - now

  • Sr. Staff Logic Design Engineering Manager / Technical Lead

    Sept 2019 - Apr 2024

  • Staff Digital Design Engineer

    May 2018 - Sept 2019

  • Staff SOC Design Engineer

    May 2017 - May 2018

  • Silicon Architecture Engineer

    Oct 2015 - Apr 2017

  • Staff IP Logic Design Engineer

    Jul 2008 - Sept 2015