HungChih Chen

Experience

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  Industrial Technology Research Institute (ITRI)(工業技術研究院, 工研院)

  Oct 1998 - May 2005

  Associate Design Engineer

  Biomedical Engineering Design an IEEE 1394 controller (implemented with verilog) and it’s test env. ,and implement on Altera FPGA for a ultrasonic medicinal imaging system Implement an HIS (Hospital Information System)info exchange App for VGHTPE(Veterans General Hosptial Taipei) , for exchanging patients medical record in between systems SDR (Soft radio) ic designer .implement / verification. On 3GPP MPS/AGC/AFCdesign blocks ,ISO7816 T1/2 protocols

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  Sunplus

  Aug 2005 - Jun 2011

  Sr. Engineer

  1.HSDPA /ASIC IP design/verification2.Mobile TV /ASIC IP Verification 3.2G Coprocessor Design/Verification 4.Audio processor verification5.DigRF Transceiver IP FPGA Design/Verification6.Chip integration.RTL/Synthesis/PT sign off/LEC check

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  Western Digital(Formal STEC)

  Jul 2011 - May 2012

  Sr. Staff Engineer - ASIC Verification

  SAS3 Controller Verification ( UVM verification)

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  新思科技股份有限公司

  Dec 2018 - now

  Sr Manager

  1.Core Technical Skills Simulator VCS expert support -UVM / Performance tuning VIP support -SAS/PCIE//SATA Gen3 VIP/IIP integration for customer support Formal Verification -Synopsys VCF support for Meditek/RealTek Verficantion planning and Architect2.Lead internal Verification projects ,End-to-End solution on arm cox with Synopsys ddr IIP/AMBA vip3.Synopsys Taiwan CES UVM instructor4.Support Synopsys formal verification solution 5.Team manager /TPM Lead an expert AE team covering Synopsys tools on VCS/Verdi/VIP/VC spyglass /Zoix /PSS Technical Program Manager for planing and execution for Synopsys new tech. deployment and landing Show less