Sang Min Lee

Experience

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  Science and Engineering Services, LLC

  Jan 2000 - Oct 2008

  Supervised/developed electronics for the fluorescence portable digital lidar (FPDL) under the Joint Biological Standoff Detection System (JBSDS) Program. Supervised/developed electronics for the atmospheric pressure matrix-assisted laser desorption/ionization - pulsed dynamic focusing (AP-MALDI PDF) system. Developed a main RF generator for a mini-bio-ID mass spectrometer. Developed a miniature mass spectrometer electronics prototype for the NASA Mars Organic Molecule Analyzer (MOMA) intended for the European Space Agency (ESA) ExoMars mission in 2013. Show less

  • Consultant

    Aug 2005 - Oct 2008

  • Senior Electrical Engineer

    Jan 2003 - Jul 2005

  • Junior Electrical Engineer

    Jan 2000 - Dec 2002
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  Georgia Institute of Technology

  Sept 2005 - Dec 2010

  Research Assistant
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  Qualcomm

  May 2010 - Mar 2017

  Design lead for a 13bit I/Q DAC with digital calibration and delta-DAC support for a wireless transceiver in 14-nm FinFET process. Design lead for master bias, process monitor, and RC monitor circuits in RF chip. Development of a 14bit I/Q DAC with calibration for an LTE support modem in 14-nm FinFET process. Development of a 14bit I/Q DAC with calibration for a wireless transceiver in 28-nm process. Development of a 14bit I/Q DAC with calibration for an LTE support modem in 20-nm process. Development of a 14bit I/Q DAC with calibration for an LTE support modem in 28-nm metal gate process. Evaluation of the new baseband filter architecture with a low voltage DAC for a future RF chip. Support and improvement on measurement for the envelope tracking DAC in 28-nm process. Minimization of DAC TX leakage to LTE receive bands. Verification on the 28-nm composite TV analog core. Enhancement and verification on switch driver clock-to-Q delay for the 28-nm wideband calibration DA. Analysis on new wideband DAC architectures such as partial swing technique or local attenuator scheme. Proposed a new switch driver for a DAC to minimize clock-to-Q delay variation with proposed DDNL analysis methodology. Analysis and verification of clock random and deterministic jitter impact on a DAC. Analysis on CORDIC tone generator performances.

  • Senior Staff Engineer

    Apr 2016 - Mar 2017

  • Staff Engineer

    Apr 2013 - Mar 2016

  • Senior Engineer

    Jan 2011 - Mar 2013

  • Interim Engineering Intern

    May 2010 - Dec 2010
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  Samsung Electronics

  Apr 2017 - Aug 2020

  Principal Engineer

  Design lead for an analog-to-digital converter, a digital-to-analog converter, and a phase-locked loop in the TSMC 12-nm FinFET process with the sampling rate of 16GS/s for the next generation 5G direct-RF/IF sampling transceiver with digital front end (DFE) which covers both sub-6GHz and mmWave basestation applications. Design lead for analog baseband circuits with instantaneous bandwidth of 1.4GHz for 5G base stations. Designed a programmable gain amplifier with 1dB bandwidth of over 700MHz. Helped on optimization and implementation of a passive low-pass filter with an integrated inductor. Show less

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  FuriosaAI

  Nov 2020 - now

  Vice President of Hardware Product Engineering

  Chip lead and project manager for the next generation inference NPU in 5nm with HBM3. Engineering lead for SI/PI/thermal and board design. Developed hardware and managed production/qualification for an NPU in 14nm.