DEEPAK BHADU

Experience

• 

  NIT Kurukshetra

  Jul 2017 - Jul 2019

  Research Scholar
• 

  VLSIGuru Training Institute

  Jul 2019 - Dec 2019

  Physical design Trainee

  During this period , worked on Full PnR flow using synopsys ICC tool .The tasks handled were Floor Planning, Place & Route of the design, perform Timing analysis usingPrimeTime. Block is timing and congestion critical (GRC, pin density and Cell density). Perform ECO iteration to fix timing violations using Prime Time.

• 

  Cadence Design Systems

  Jul 2020 - now

  1. Handled block level physical design implementation starting from synthesized netlistto GDS-II, meeting PPA.2.Contribute in Voltas flow setup to perform Power analysis checks IR/EM at Top level. Experience in performing IR /EM anlaysis for multiple PHY IP.understanding of Full chip IR & STA flow .3. Responsible for PHY TOP PNR activities.4. Basic understanding of 3DIC IREM flow 1. During internship period worked on Cadence first 12LP/LP+ memory IP solution. https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr/2020/cadence-announces-broad-ip-collaboration-with-globalfoundries-on.html2. Executed Block level PnR for 3 slices .Responsibilities:- Performed PnR, LVS, DRC, Sign-off timing closure, Power and IR analysis3. successfully tapeout 2 projects during internship duration.

  • Design Engineer 2

    Jun 2021 - now

  • Design Engineering Intern

    Jul 2020 - May 2021