Yu-Hsiu Ho

Experience

• 

  TSMC

  Jan 2013 - Oct 2014

  Dry Etching Process Engineer

  • Boosted production capacity by certifying new tool• Monitoring the manufacturing process by statistical process control

• 

  BASF

  Nov 2014 - May 2016

  Lab. Management Engineer (Adv. Cleaning, Etching & Photo Ancillaries)

  • Established wafer level product validation test for semiconductor chemicals.• Single-wafer cleaning tool Validation for wafer-level test (SEZ SP304).• Lab. process tool maintenance.

• 

  Ever Pure Applied Material Co., Ltd

  Jun 2016 - Dec 2017

  Customer Service Manager

  • Provide filtration solution for FPD, petrochemical and drinking water industry• Packaging material valuation and Steam sterilization validation for sterilizing-grade filter using in pharmaceutical industry.

• 

  MSSCORPS 汎銓科技

  Mar 2018 - Nov 2024

  • Identified the anomaly that caused leakage in read/erase process utilized by OBIRCH/decapping/ Nanoprobe/TEM for the 3rd generation SuperFlash (ESF3), finally help client raising 1% yield rate.• Investigated the failures, such as forming/reset fail, leakage and open, in ReRAM which failed in read/write test via decapping/SEM/FIB/TEM/EDX and help improve the yield rate and reliability.• Established an analytical solution for re-deposition in MRAM etching process by FIB/TEM/EDX, assisting client to develop etching strategy and boost process development.• Enhanced the reliability of PCRAM via identifying the segregation in phase change material during manufacturing process by use of TEM/EDX.• Investigated the peeling, bubble, blister, crack, chipping and debonding in wafer-on-wafer or die-on-wafer bonding process used for 3D stacked CIS/CMOS chip through CSAM/SEM/FIB/TEM/EDX to reduce defect rate.• Analyzed the root cause of open/high-resistance in Through-Silicon Via (TSV) and hybrid metal bonding for multi-stacked 3D packaging die by virtue of decapping/SEM/FIB/TEM/EDX and fixed the weakness of product.• Inspected the bubble in the polyimide between RDL for FOPLP process, and figure out the formation resulted from contamination by FIB/TEM/EDX. It helped process improvement and benefited product reliability.• Identified the microvoid/open in blind via of PCB which failed in the thermal cycling test through FIB/TEM/EDX, and eliminated the risk in chemical/electrical deposition process and improved reliability.• Investigated open/crack in wire-bonding interface for the MEMS after HTOL test via SEM/EDX. The failure might be induced by electromigration, thermal aging and the IMC formation. The finding is useful to optimize FMEA and improve product reliability.• Solved electrical leakage in WAT by finding out the impurities in spin-on dielectrics between intermetal and the impurities released from valve in track system by GC-MS, finally increase the yield rate. Show less

  • Assistant Technical Manager

    Jun 2022 - Nov 2024

  • Staff Engineer

    Jul 2021 - Jun 2022

  • Senior Materials Analysis Engineer

    Mar 2018 - Jun 2021
• 

  TSMC

  Nov 2024 - now

  Customer Service Manager

  • Provide wafer foundry and packaging service and collaborate with customers in Asia-Pacific region to success in business.