Neha Joshi

Experience

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  Modi Institute of Technology,Kota

  Jul 2001 - Apr 2005

  Lecturer

  Coached engineering students for Electronics and Digital Electronics subjects.Was responsible to set up all the Electronics/Digital Electronics practical labs.

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  Cadence Design System

  Jan 2005 - Jan 2010

  Application Engineer

  Worked on Conformal Logic equivalency checker, Encounter RTL Compiler (Synthesis)

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  CMC

  Nov 2005 - Oct 2010

  IT Engineer

  Placed on onsite project in EDA company, Cadence Design System in Front End group. Working as Application Engineer.

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  Sasken Communication Technologies Ltd

  Oct 2010 - Mar 2013

  Lead Design Engineer

  Worked on CORTEX A5 Dual ( Frequeny of 600 MHz at 40 nm technology) and Single core (700 MHz at 28 nm technology) , ARM 946 ( 300 MHz at 40 nm technology) and ARM 926 ( 300 MHz at 40 nm technology). synthesis, timing, verification, DFT, ATPG.Setting up environment for Synthesis, including checking and setting for various parameter required to be used for as per SOW. Optimization of the given RTL, writing out design and timing constraints for the complete design at integration level. Analyzing the timing reports, (Area reports for comparison with some previous cores) and meeting the timing by using various techniques like checking for false paths, MCP, any generated clocks to be used, checking with input output delay, grouping, twisting latency. Show less

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  Cadence Design Systems

  Jun 2013 - now

  • Education Application Engineer Architect

    Jul 2024 - now

  • Sr Principal Education Application Engineer

    Jul 2019 - Jul 2024

  • Principal Education Application Engineer

    Jul 2016 - Jun 2019

  • Technical Education Consultant

    Jun 2013 - Jun 2016