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Naga Sai Theja Malipeddi

Naga Sai Theja Malipeddi

IEEE member

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location of Naga Sai Theja MalipeddiBrunswick, Lower Saxony, Germany

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  • Timeline

  • About me

    Senior Physical IC Design Engineer at Coherent | MSc grad in Nanoelectronic Systems

  • Education

    • NRI junior college vijayawada

      2012 - 2014
      11th,12th standard MPC 97.3%

    • Sri vani high school

      2011 - 2012
      10 th standard SSC 9.5

    • Technische Universität Dresden

      2021 - 2023
      MSc Nanoelectronic systems 2.0 (highest 1, lowest 5)

      Hardware Modeling and SimulationVLSI Processor DesignPhysical Design Embedded Multi-core ArchitecturesHardware Software Co DesignSemiconductor TechnologyInnovative Semiconductor DevicesPrinciples Of Dependable SystemsRadio Frequency Integrated CircuitsMolecular ElectronicsProject : Glitch power analysis of digital integrated circuits at RTL and (Place and route) levelMaster Thesis : Physical implementation of LDPC ECC utilising 22 nm FDSOI… Lihat selengkapnya Hardware Modeling and SimulationVLSI Processor DesignPhysical Design Embedded Multi-core ArchitecturesHardware Software Co DesignSemiconductor TechnologyInnovative Semiconductor DevicesPrinciples Of Dependable SystemsRadio Frequency Integrated CircuitsMolecular ElectronicsProject : Glitch power analysis of digital integrated circuits at RTL and (Place and route) levelMaster Thesis : Physical implementation of LDPC ECC utilising 22 nm FDSOI adaptive body biasing. Lihat lebih sedikit

    • Vellore Institute of Technology

      2014 - 2018
      Bachelor of Technology (BTech) Electrical, Electronics and Communications Engineering 9.21

      Aktivitas dan Kegiatan Sosial:IEEE MTTS project head, Dance club member

  • Experience

    • IEEE

      Sept 2015 - Mar 2018
      IEEE member

      In September 2015, I started my role as a Project Head at IEEE MTTS, where I gained valuable experience in project management. As a member of the project team, I actively contributed to projects involving IoT, Arduino, and WiFi modules. One notable accomplishment was the development of a cost-effective smart dust bin, which facilitates garbage collection and sorting using an Arduino, a WiFi module, and a web interface. This innovation addresses the waste management challenges faced by large industries, companies, and institutions by enabling remote monitoring of waste levels via a webpage from a central location. Lihat lebih sedikit

    • BSNL Telecom Factory

      Jan 2016 - Jan 2017
      Internship

      Received training on Telecom Technologies such as GSM, Broad band, Transmission.Gained knowledge and hands-on experience on Computer networking concepts namely Switching, IP Addressing, Routing.Gained knowledge in Mobile Communication Systems and Digital Transmission Systems

    • Electronics Corporation of India Limited (ECIL)

      Jan 2016 - Jul 2016
      Summer Internship

      Received intense training and working experience on Hardware description languages like VHDL and Verilog

    • IQVIA India

      Jun 2018 - Nov 2020
      Software Engineer

      • Two and half years of empirical experience in the field of ETL and Data Warehouse Testing• Test, validate and troubleshoot system configurations with API based integration technologies• Use Amazon S3 buckets to load fact and dimensional data via ETL into a Cassandra database• Troubleshoot logs generated by Kibana, Hadoop MapReduce, Reltio, Qubole and Informatica.

    • Deveritec GmbH

      Jan 2021 - Nov 2021
      Working Student

      Digital Design (FPGA Design using Verilog and VHDL).Implementation and Routing tasks.Validation of FPGAProtocal : AXI QUAD SPIADC : ADC9257FPGA : Xilinx ZYNQ 7000 Artix-7

    • Racyics

      Jan 2022 - Sept 2024

      Technology: 22nm FDSOI (Global Foundries) Technology: 22nm FDSOI (Global Foundries)

      • Physical IC Design Engineer

        Nov 2023 - Sept 2024

      • Working Student

        Jan 2022 - Jan 2023

    • X-FAB

      Jan 2022 - Feb 2022
      Working Student

    • Coherent Corp.

      Jan 2024 - now
      Senior Physical IC Design Engineer

      Technology: 3nm FINFET (TSMC)

  • Licenses & Certifications

    • Peer Teach Series Workshop

      School of Electrical Engineering Of VIT
      Sept 2016
      View certificate certificate

    • Joules Power Calculator v20.1 Exam

      Cadence Design Systems
      Mar 2022
      View certificate certificate

    • Innovus Block Implementation with Stylus Common UI v22.1 Exam

      Cadence Design Systems
      Feb 2023
      View certificate certificate

    • Innovus low-power flow with stylus common ui 21.1

      Cadence Design Systems

    • Basic static timing analysis

      Cadence Design Systems
      Sept 2022

    • Virtuoso Layout Design Basics vIC6.1.8 Exam

      Cadence Design Systems
      Jan 2022
      View certificate certificate

    • Cadence RTL-to-GDSII Flow v3.0 Exam

      Cadence Design Systems
      Nov 2022
      View certificate certificate

    • TCL2: Creating procedures

      Synopsys Inc
      Feb 2023
      View certificate certificate

    • TCL1: Becoming a proficient user

      Synopsys Inc
      Feb 2023
      View certificate certificate

    • VLSI Design using Verilog HDL - Workshop

      Maven Silicon
      Jan 2019
      View certificate certificate

  • Honors & Awards

    • Awarded to Naga Sai Theja Malipeddi
      Runner up in IQVIA Foosball championship 2019 IQVIA Sep 2019
    • Awarded to Naga Sai Theja Malipeddi
      Standing Ovation Award IQVIA Aug 2019