
Mohammad Shafkat M Khan
Program Committee Chair

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About me
Former GPU RTL Design Intern @ Nvidia | Former GPU Performance Analysis Intern @Intel | PhD Candidate @ University of Florida
Education

Willes Little Flower School and College
2012 - 2014A Level Science 4A* and 1A
Willes Little Flower School and College
2001 - 2012O Level Science 6A* and 2AActivities and Societies: President of Willes Community Service Club

University of Florida
2021 - 2025Doctor of Philosophy - PhD Electrical and Electronics Engineering
University of Florida
2021 - 2023Master of Science - MS Electrical and Electronics Engineering 3.86/4.00
Bangladesh University of Engineering and Technology
2015 - 2019Bachelor of Engineering - BE Electrical and Electronics Engineering
Experience

IEEE BUET Student Branch
Feb 2018 - Apr 2019Program Committee Chair
IEEE Bangladesh Section - SAC team
Mar 2018 - Mar 2019Content Writer
IEEE RAS BUET
Jun 2018 - Apr 2019Chair
IEEE Bangladesh Section
May 2019 - Dec 2019Publicity Sub-Committee Member
Keystone Business Support Company Ltd.
Sept 2019 - Mar 2020Technical Associate
University of Florida
Jan 2021 - nowResearch AssistantEmployed as a graduate research assistant at Florida Institute of Cyber Security (FICS). FICS has the largest research group focused on cyber security in North America. We are frequently collaborating with government bodies, department of defense, and private semiconductor and software companies, developing solutions and prototyping on FPGAs. Current responsibilities include: i) leading a US Navy funded project on security of HPC heterogeneous ICs, ii) investigating physical inspection modalities to facilitate failure analysis and defect localization in advanced package ICs. iii) Enabling secure boot in System-in-Package and System-on-Chip Show less

Intel Corporation
May 2022 - Aug 2022GPU Performance Analysis Intern- Part of the AXG Group working on performance verification of HPC GPU- Performance profiling and debugging for design optimization- Develop tools to facilitate and automate performance verification workflow - Work in conjunction with RTL team, and performance team to provide solutions to problems that slow down workflow- Understand GPU architecture, low level and high level performance counters to build more proficient profiling tools. - Data analysis and profiling using OOP, packages such as pandas and numpy- Python scripting, software development (front-end and back-end), implementing APIs , GUISkills: Microarchitecture · Performance Verification · Data Profiling · Kivy · Pandas (Software) · Graphics Processing Unit · Tkinter · High Performance Computing (HPC) · Python (Programming Language Show less

Intel Corporation
May 2023 - Aug 2023GPU Performance Intern- Part of the AXG Group working on performance verification of HPC GPU- Collaborating with RTL team to localize performance bottlenecks, and implement mitigation- Comprehend the memory hierarchy in an architecture and profile memory pipeline utilization of different workloads.- Develop tools to facilitate and automate performance verification workflow - Understand GPU architecture, low level and high level performance counters to build more proficient profiling tools. - Data analysis and profiling using OOP, packages such as pandas and numpy- Develop full-stack software solution to accelerate performance debugging workflow Show less

NVIDIA
May 2024 - Aug 2024ASIC Design & Verification Intern (GPU)-Develop an understanding of the cache micro-architecture hierarchy, coherence and policies.-Design and implement low power techniques to cache memory subsystem of data center graphics processors.-Optimize control flow in L2 cache pipelines to improve dynamic power efficiency. Understand and apply credit-based flow control mechanisms through datapath in the memory subsystem.-Develop RTL code for proposed design change using System Verilog. Integration of new IP block into existing hierarchy, and debugging regression errors on Verdi. Understanding of ASIC design flow.-Execute logic synthesis, run power stimulus regression, estimate area overhead of proposed IP design change.-Assess the impact of proposed change on L2 power across workloads. Result: 1-5 percent possible improvement. Show less
Licenses & Certifications
- View certificate

Verification Series Part 4: UVM Projects
UdemySept 2025 - View certificate

Verification Series Part 3: UVM Essentials
UdemyMar 2025 - View certificate

SystemVerilog for Design and Verification v25.03 Exam
CadenceDec 2025
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