Chee How Goh

Experience

• 

  Intel Corporation

  Dec 2001 - Nov 2021

  Managing and leading the programmable solution design verification (DV) organization comprising IPs and subsystems, i.e. PCIe Gen X, Ethernet, PTP, Interlaken, Serial Lite IV and various 5G IPs (JESD204B/C, CPRI, eCPRI, ORAN) to ensure high quality soft IPs, subsystems and solution to enable growing market in data center, 5G, cloud computing and edge computing areas.• Orchestrate the DV organization, delivering (verifying) quality IPs and solution through multiple programs (Stratix10 and Agilex families) and Quartus releases every Quarter.• Driving division level consistent DV collaterals (standardized Testplans/VIPs/BFMs) across organization on FPGA IP Solution verification and Hardware Example Design validation. • Continue to expand more IP DV methodology (System Verilog UVM, constrained random tests generation though functional/code coverage, XPROP, Formal Verification etc.) to be scalable and reusable across subsystems and shells Show less Managed and led the Chipset SOC Front End Design teams (RTL, Integration, Design Verification) in various technical leadership roles driving complex features to Tape In for multiple generations of Intel Chipset Products (Tiger Lake PCH, Ice Lake PCH, Comet Lake PCH, Cannon Lake PCH etc.)• Led multiple SOC programs that integrated multiple IPs (PCIe, USBx, eMMC, UFS, NAND, Gbe, TSN, SATA, CNVi, SPI, Display etc) co-developed by multiple geographically dispersed teams in US, Malaysia and India. • Managed RTL design and Design verification team and collaborate with stakeholders to integrate and validate RTL at Full-chip and System level in an extensive matrix structure.• Led division level initiative to standardize methodologies (FCP, OVM, XPROP etc.) to develop, integrate and verify design IPs for efficiency, quality and schedule imperatives. Show less

  • FPGA Design Verification Senior Manager/Director

    Apr 2019 - Nov 2021

  • ASIC SOC Design Engineering Senior/Staff Manager/Leader

    Apr 2015 - Mar 2019

  • ASIC IP Design Engineering Staff/First Line Manager/Leader

    Apr 2008 - Mar 2015

  • ASIC IP Design & Verification Junior/Senior Engineer

    Dec 2001 - Mar 2008
• 

  Nokia

  Dec 2021 - now

  SOC IP HW Project Manager