Raqqib Bin Kadir

Experience

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  ULKASEMI LIMITED

  Dec 2014 - Jun 2016

  IC Layout Design Engineer

  • Experienced in Designing & working on Full Analog & mixed signal Block from transistor level to chip level.• Familiar & have experience is working on various technology node & PDK upto 10nm. • Efficient in working on cell Floorplan & powerplan.• Very Good Understanding on Memory Cell, bit cell,SRAM memory architecture.Hand on experience on layout Techniques of Band-gap, current mirror,Differential Pair, device matching , common centroid design.Efficient in solving antenna, ESD , Latch up errors. • Experience in IC physical design(floor plan, Placement, Routing, Clock Tree Synthesis, TimingClosure)• Strong Layout verification skill as LVS, DRC, DFM.• Tools: Virtuoso Schematic Editor, Virtuoso Layout Suite, Calibre DRC™, LVS,xRC™ and Calibre RVE™,Cadence® Allegro® PCB Designer, OrCAD® PCB Designer, Cadence Encounter Tool,Proteous, HSPICE.• Programming & scripting languages: C++, C, Verilog-HDL,system verilog, python, pearl, unix, shell. Show less

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  Walton Group

  Jul 2016 - Aug 2022

  Senior Additional Director (Senior Product Manager)

  • Responsible for overall operations to ensure sustainable growth, achieve the business target and maintain continuous process development.• Develop, manage & and analyze the market for Innovative new products for the Market. Define product strategy and roadmap.• Development of computer Motherboards, DDR4/DDR5 DRAM, Solid state storage devices, andportable power storage systems• Work closely with engineering teams to understand platform capabilities,limitations, and architectural considerations• Generate design concepts, wireframes, and prototypes that consider both user experience and technical constraints.• Study/Bench-marking/Reverse engineering of the competitor product Show less

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  TETON

  Sept 2022 - now

  Senior Project Manager (IC Physical Design)

  • Analyze system requirements, customer needs, and design constraints to determine project feasibility in IC physical design and AMS custom layout.• Define and develop chip architecture, including subsystem integration, floorplanning, and design partitioning for ASIC/SOC.• Perform RTL-to-GDSII implementation, covering synthesis, placement, clock tree synthesis (CTS), routing, and timing closure.• Optimize power, performance, and area (PPA) while addressing design for manufacturability (DFM) and process variation challenges.• Execute full-custom layout design for Analog and Mixed-Signal (AMS) circuits, ensuring compliance with DRC/LVS/ERC rules.• Conduct post-layout verification, including parasitic extraction, electromigration (EM/IR) analysis, and reliability assessments.• Collaborate closely with circuit, verification, and foundry teams to meet design specifications and ensure first-pass success.• Support tape-out activities, debug silicon issues, and work with foundries to optimize process technologies for advanced nodes. Show less