Hennadii Z.

Experience

• 

  Aldec

  Sept 2012 - now

  C++ Developer

  Project Description: Cross-platform linting tool for different FPGA/ASIC designs with advanced UI and editor. It supports VHDL, Verilog and SystemVerilog. Solution is focused on general issues analysis including: more optimal synthesis results that match simulation, avoid different potential problems, code portability and reusage. In addition, it has TCL scripting support and RTL schematic viewer.Key Responsibilities:- Syntax and semantic analysis of VHDL and Verilog languages;- Implementation of design rule checkers for code to spot different issues according to different guidelines;- Integration with various 3rd-party libraries and additional fixes;- Database improvement;- Reports generation (in txt, CSV formats);- Build process maintenance;- Code refactoring;- Performance optimization;- Code reviewing. Показати менше

• 

  Freelance

  Jan 2016 - Jan 2017

  Software Developer

  Register level (RTL) coverage analysis tool for VHDL/Verilog.

• 

  SoftServe

  Jan 2017 - now

  Porting graphics editing application to web. Leading a small team of developers. New features development for graphics editing applications. Porting graphics editing applications to Mac.

  • Lead Software Engineer

    Apr 2022 - now

  • Senior Software Engineer

    -

  • Software Engineer

    Jan 2017 - now