Rajesh Wasnik

Experience

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  Tejas Networks

  Jan 2006 - Jan 2008

  R&D Engineer

  Coded RTL for design enhancements and bug fixes for SDH/SONET based communication equipment. Design was developed using Verilog and verification was done on target FPGA device after synthesis.

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  NXP acquires Freescale Semiconductor

  Jan 2008 - Jan 2011

  Senior Design Engineer

  Verified couple of IPs used for control and data path of networking chips. Serial RapidIO (SRIO) based message communication protocols were used in these IPs. Unit level verification was done using SV and proprietary SVBCL methodology of Freescale.

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  Intel Corporation

  Jan 2011 - Jan 2017

  Pre-Silicon Verification Engineer

  Verified Omni-Path Interconnect Architecture based Adapters and Switches for High Performance Computing (HPC) applications. Developed verification infrastructure for omni-path based host fabric interface (HFI) using SV and UVM. This involved coding of various verification components like fabric side FLIT based protocol packet items, interface monitors, drivers, scoreboards, reference models (checkers) and traffic sequences. Completed verification, debugging and development for data path, control path and error logic of the HFI at core-level as well as sub-system. Supported SoC teams in path clearing system level verification. Show less

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  Qualcomm

  Jan 2017 - Jan 2020

  Staff Engineer

  I was part of Subsystem Verification Team as technical lead for Qualcomm’s ambitious AI Inference Accelerator Chip.Key responsibilities:- Scope projects with managers (analysis of design architecture, feature enhancements, change requests, reusability of testbenches and effort estimation) - Write testplan and develop testbench architecture, agents and other verification components based on the requirement. - Stimulus / sequence development as per planned test scenarios and debug for finding bugs in the design in order to deliver functionally working subsystem.- Coverage analysis to identify and fill coverage holes before marking completion of the project.- Help team members in resolving technical issues and roadblocks.Last project:- Verifying neural signal processing subsystem. Mainly looking at the DSP processor and datapath side of things for inference application. Testbench is developed using UVM and proprietary Native flow methodology of Qualcomm. Stimulus is being developed using SV and C.Previous project:- Verified interrupt controllers in processor subsystem for ARM based server project. It was quite a complex chip with 96 cores and 50 billion gate counts, couple of variants of this server chip has been verified one after the other. Flow of Interrupt (SPI/SGI/PPI/LPI) and configuration path was verified thoroughly using Qualcomm’s Native flow methodology. Show less

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  Cadence Design Systems

  Jan 2020 - now

  Technical Lead for CXL HPA Controller IP design verification efforts.Managing IPG (Noida) DV Team.

  • Design Engineering Architect

    Jul 2022 - now

  • Sr. Principal Design Engineer

    Jan 2020 - Jun 2022