Muhammad Amir Altaf

Experience

• 

  PCSIR

  Sept 2018 - Oct 2018

  Internship

  Participated in day to day operations and learned procedures of repair and maintenance of walk through gates, Hand Metal Detector, Uninterrupted Power Supply (UPS). Thoroughly studied Function Generator, Laboratory Equipment and Integrated Circuits (IC’s).

• 

  Ufone MSC-CDAS

  Nov 2019 - Jan 2020

  Engineer Intern

  Learned how to access the Base Transceiver Stations (BTSs) and Base Station Controllers (BSCs) remotely in order to rectify the service affecting alarms

• 

  Lampró Méllon

  Jan 2020 - Dec 2021

  Major responsibilities include:• Onboarded & Verified Synopsys DMAC-IP on RISC-V based SoC - Developed the UVM-VIP to verify DMAC-IP on SoC Level - Developed C-tests targeted to check features supported by DMAC-IP - Used Mailbox methodology as synchronization between C-test environment and UVM Environment - Developed assertions to verify the functionality - Developed the exclusions, and completed functional coverage • Worked on the Coverage Closure of eMMC on SoC Level - Developed C-tests to toggle the error-related signals of eMMC - Developed C-tests targeting physical layer registers of eMMC Show less • Worked in a team on various projects and learned how to collaborate in a team to complete the projects and meet the deadlines• Gathered Hands-on experience with Industrial standard Design and Verification Projects - Developed a UVM-VIP and Reference Model (RV32I) for the verification of Load-Store Unit (LSU) of SweRV EL2 core - Developed a MAS for Breakpoint Unit by reviewing the open-source SiFive E21 document and, designed the Breakpoint Unit in SystemVerilog and verified its functionality - Designed a RISC-V three-stage pipelined processor - Developed a reference model with RV32I support for RISC-V SweRV EH1 core - Designed and integrated a simplified D-cache in SweRV EH1 core - Designed a layered-testbench environment for the verification of Tilelink-UL Slave protocol Show less

  • Associate Design Verification Engineer

    Oct 2020 - Dec 2021

  • Trainee Engineer

    Jan 2020 - Sept 2020
• 

  RapidSilicon

  Dec 2021 - Mar 2023

  Design Verification Engineer

  • Currently working on a coverage enhancement project; includes coverage closure targets, and GLS simulations• Conceptualized the three conformance levels (TL-UL, TL-UH, TL-C) of TileLink

• 

  Axiomise

  Apr 2023 - now

  • Senior Formal Verification Engineer

    Jul 2024 - now

  • Formal Verification Engineer

    Apr 2023 - Jul 2024