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Yashas Chiniwalar

Yashas Chiniwalar

Intern

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location of Yashas ChiniwalarBengaluru, Karnataka, India

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  • Timeline

  • About me

    Trained ASIC Physical Design Engineer at ChipEdge | Reva University

  • Education

    • REVA University

      2019 - 2023
      Bachelor of Technology - BTech Electronics and Communications Engineering

    • CMR Group of Institutions

      2017 - 2019
      Pre-University Course- Physics, Chemistry, Mathematics Electronics

    • Legacy School Bangalore (LSB)

      2010 - 2017
      High School Science 67.93%

      Activities and Societies: Team Leader for house Foot ball team House President

  • Experience

    • Farmizen

      Apr 2018 - Apr 2018
      Intern

      Worked as intern in developing and using drones in farming and collecting data about crops pushing it to cloud for further analysis

    • REVA University

      Apr 2022 - Apr 2023
      President

    • Tech Mahindra Cerium Pvt Ltd

      Jan 2023 - Apr 2023
      Intern

    • Astronics Test Systems (formerly Diagnosys)

      Jun 2023 - Nov 2023
      Application Engineer

      Worked as Application Engineer to develop efficient test strategy for golden PCB boards from customer by circuit analysis to determine best possible way for fault detection and isolation.

    • ChipEdge Technologies Pvt Ltd

      Jan 2024 - Jul 2024
      ASIC Physical Design Trainee

      Gained extensive knowledge in ASIC flow and Physical design flow, working on projects like ChipTop, JBI and falcon based on 14nm and 28nm technology nodes. Adequate tools exposure in Synopsys Design Compiler, IC Compiler, StarRC and Primetime.

  • Licenses & Certifications