Steve Park

Experience

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  Dongbu HiTek

  Jul 2000 - May 2016

  Senior Manager

  Rich experience in etch process in Dongbu Hiteck(2000.07 ~ 2016.05) - Set up the Etch equipments (LAMRC HPT & DFM, TEL DRM & SCCM, AMAT DPS & DPS2 & etc.) - Developed the new etching process recipe. (Poly, Dielectric & Metal etch) - Settled the Cu damascene process with LAMRC HPT & TEL SCCM dialectic ETCHER. - Managed etching process through the Output data (IQC, EQC, Defects, FDC & etc.) - Reduced production cost by cost reduction activity (diversification of gas and parts vendor & etc.) * Prolonged the life time of SI Cell & Focus Ring of TEL SCCM OXIDE ETCHER * Diversification of parts of TEL SCCM & AMAT DPS Etcher * Changed the Etch process gas (C5F8 -> C4F8) at oxide etch * Diversification of Etch process gas (C4F8, BCl3, HBr etc.) - Improved the quality of IC Chip with various activities (M/C modify, Optimization of parts lifetime and etc.) - Increased the productivity by Etch process modification. - Set-up the high performance oxide etch process (@TEL SCCM & LAM HPT) - Optimize the Metal etch process using AMAT DPS METAL ETCHER - Managed and analyzed the defects induced by FAB Processing with KLA-Tencor’s wafer Inspection equipment and Klarity tool. - Made faster yield improvement through defect analysis (with Klarity, YMS, FDC & etc.) to CIS, FLASH, LOGIC,LDI Chip & etc - Monitored the abnormal FAB processing with FDC & Warned the abnormal M/C signal. - Monitored the IQC (CD, Overlay, Thickness & etc) & EQC (M/C Particle, Etch rate and etc.) data and Warned the abnormal signal. - Analyzed the low yield wafers using Klarity, FDC, YMS tools and etc. - Verified the recipes of patterned & unpatented wafer inspection equipment. - Lectured the Six Sigma methodology in the capacity of in-house instructor. - Performed 3 BB Projects for over a year and a half. - Guided the several GB(Green belt) projects. Had Trouble – shooting experience - Solved many low yield issue (hole not open issue & etc) Show less

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  Applied Materials

  Aug 2016 - Apr 2017

  BD Manager

  Development of parts businese for the Samsung Electronics.

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  Brain202 Co., Ltd.

  Oct 2017 - Feb 2018

  Director

  Charged in Semiconductor department

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  ON Semiconductor

  Feb 2018 - now

  부장

  Etch process development eng'r.I am now supporting the SIC MOSFET device.- M3 SiC Oxide dry etch processes development with LRC RBW and TEL DRM. : High selectivity oxide etch recipe (to SiN, Ni silicide and TiN) process set-up : Good shaped IMD (NO and Only oxide) spacer etch set-up : The SiC CNT Oxide etch set-up- SiC Trench etch process development with TEL UD. : Good U/F trench etch process set-up with SiF4 : Dual hard mask trench etch set-up