Experience

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  Candela microsystems (s) pte ltd, singapore

  Aug 2005 - Mar 2012

  Design engineer

  • Experience in various phases of product - behavioral description, architectural definition, design, planning, coding, Verification, Static Timing Analysis and physical design.• Worked on FPGA and ASIC designs, RTL and gate level coding.• Performed Top level resource and timing allocation.• Created block level designs and Integrated block level designs into the top-level design.• Created test benches including behavioral modes for analog blocks and external components.• Simulated designs for functional and timing verification.• Created ASIC library data for physical verification and implementation.• Created physical and timing constraints for Place & route, timing analysis and implementation.• Performed Place & Route, Clock tree synthesis, Timing analysis and Physical signoff.• Performed Top level placement and routing with cross talk reduction and skew balancing.• Created automation tools for speeding up tasks and analysis.• Algorithm design and quick verification using Matlab, GNU Octave, C and C++• Designed PCB and perform board level testing with use of Oscilloscope and Logic analyser.• Assisted in patent search tasks.• Provided documentation and training to the new comers for the project.• Worked on I2C, SD card, FAT file system, JPEG and MPEG2 standards.• Worked on DDR and DDR2 interfaces. Show less

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  Marvell semiconductor

  Feb 2013 - Apr 2017

  Staff, asic design engineer

  • Analysis of Subsystem Micro - architectecture before the design and integration phases.• Interact with architecture team, integration team and other IP designers to clarify, optimize and avoid future issues across interfaces within the subsystem and at SoC level.• Plan and discuss interface of own handling IPs with integration team before the actual RTL design process.• Development/Enhancement of various Video pipeline IPs for various SoCs from a given C-algorithm / specification through Area estimation, Verilog RTL design, IP level C-RTL verification setup and verification.• Perform IP level Synthesis, FV and CDC runs before delivering the IPs to the integration team on time.• Review and optimize legacy IPs’ for area and performance.• Review other IP designer’s IP architecture and RTL to suggest on area and performance improvements.• Work closely with integration team to ensure one pass integration simulation checks.• Build automation scripts to assist verification at IP and subsystem level.• Integrate algorithm c-models across IPs at subsystem level to analyze pipe level functionality and to accommodate for subsystem level C-RTL verification.• Analyze and create models, test vectors for subsystem interfaces to be used at subsystem level verification.• Support across other IP designers and integration team for subsystem level verification test-bench to ensure faster verification bring up of IPs and subsystem.• Guide intern and integration team to create and improvise on bring up of functionality sanity checks. Show less

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  Intel corporation

  Apr 2017 - now

  NOC and IP Microarchitecture, RTL design

  • IP architect

    Nov 2023 - now

  • SoC Design Engineer

    Apr 2017 - Nov 2023