Sanaullah Sultan

Experience

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  Seurehopes

  Jul 2017 - Aug 2019

  Embedded Software Engineer

  Stabilizer control using PIC16F micro controller.Deadbolt automation using ESP32.GSM functionality in electronic rat board and also design it Desktop app in QT to controlremotely.Design basic PCB for isolated TTL.

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  VISpro LAB

  Aug 2019 - Mar 2021

  FPGA LOGIC DESIGN

  Encryption and Decryption of data using LFSR.FIR filter design synthesis in Verilog and MATLAB.Design Space Exploration on area, frequency and power.Generalization of Shift Register, Fast Adder, Multiplier, Processor implementation.Approximate the Design by DRUM multiplier and SMApproxLib.Cardano and Iota coins are integrated in Opolo hardware wallet cryptocurrency transaction.

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  DreamBig Semiconductor Inc.

  May 2020 - Feb 2022

  ASIC Verification Engineer

  • Python Scripting for Scapy to create custom packet and dump them in a pcap file.• Ethernet MAC IP verification in UVM from scratch also design its RAL.• Create DMA RAL, RTL and its UVM Model.• Simulation setup for Ethernet MAC with SerDies.• SPI IP verification in UVM from scratch.• SystemVerilog Assertion based verification for Packet Buffer.• FPGA prototyping for MAC with BIST for configuration using SPI interface.• Use ARM Core to program RAL of all the IP's.• RAL conversion from RALF to SystemRDL 2.0. Show less

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  Diode Solution

  Sept 2020 - now

  Self Employed

  • AES 128, 192, 256 IP architeure development.• AES verification UVM and formal verification.• DNN and FIR approximation using quantization.• RISC-V vector ISA implementation and validation.• Explore SytemRDL 2.0 to generate RTL and UVM model

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  RapidSilicon

  Feb 2022 - Jul 2022

  ASIC Verification Engineer II

  • PCIe Gen4 Subsystem functional verification for WARBOY SoC by using Synopsys VIP.• Perform test for TL layer DL layer and LTSSM.• Develop the mechanism to sink processor to the VIP.• PCIe Subsystem bring with SerDes add the SerDes firmware loading in the processorbooting process.• Interface Coverage by driving processor and VIP.

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  Rambus

  Jun 2022 - Feb 2024

  Senior Design Verification Engineer

  • RAL design and Verification for Rambus IP generator tool• PCIe verification by programing the IP multiple configuration