Gowri Ratnasri Mahendrawada

Experience

• 

  Intel Corporation

  Jan 2018 - Mar 2021

  Verification of fabric Interface of a Load balancer IP.• Working on Interface Protocol to match the Design Specification.• Written directed tests to cover the corner cases for 100% functional Coverage.• Debugging various testcase failures to deliver functionally correct design blocks.Skills : Universal Verification Methodology (UVM) • SystemVerilog • Perl . Functional Verification SoC Verification Intern • Worked on Building Strong Architecture and Design Knowledge.• Working with Architects and design engineers to understand the functionality to be verified.• Develop System Verilog Assertions for end to end functionality checks.Skills : VCS · Verdi · Linux · System Verilog . System Verilog Assertions

  • SoC Design Engineer

    Jul 2018 - Mar 2021

  • Intern

    Jan 2018 - Jun 2018
• 

  Qualcomm

  Apr 2021 - Jan 2023

  Senior DV Engineer

  Design Verification of PHY for 100G Ethernet.• Developing sequences for the SERDES features.• Integrating SERDES PHY to the testbench environment using UVM and SystemVerilog.• Worked on Creating constraint random stimuli and ran regression suites, debugged simulation failures.Skills: SystemVerilog · Universal Verification Methodology (UVM) · Functional Verification · Perl · Application-Specific Integrated Circuits (ASIC) . Formal Verification