
Freddy Alexander Forero Ramirez
Senior Customer Service Engineer

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About me
Solutions Engineer Sr Synopsys. Analog and digital IC design
Education

Instituto Nacional de Astrofísica, Óptica y Electrónica
2016 - 2020Doctor of Philosophy (PhD) Electronics EngineerActivities and Societies: Integrated Circuits Design and Test Group Thesis Title: Development of fault models and new test methodologies in Nano-metric semiconductor technologies.Design of digital integrated circuits using FinFET technology.Simulation of integrated circuits based on FinFET technology under process variations with different defects.Development of CAD tools (Python) for FinFET technology with applications for testing.Characterization and modeling of defects in VLSI digital circuits design with FinFET technology as Bridge, Full… Show more Thesis Title: Development of fault models and new test methodologies in Nano-metric semiconductor technologies.Design of digital integrated circuits using FinFET technology.Simulation of integrated circuits based on FinFET technology under process variations with different defects.Development of CAD tools (Python) for FinFET technology with applications for testing.Characterization and modeling of defects in VLSI digital circuits design with FinFET technology as Bridge, Full open and Resistive open defects.Description and characterization of new types of defects due to the double patterning techniques in digital circuits based on FinFET technology. Show less

Instituto Nacional de Astrofísica, Óptica y Electrónica
2013 - 2015Master of Science (M.Sc.) Electronics EngineerActivities and Societies: Integrated Circuit Design and Test Group Thesis Title: Robust aging circuits of NBTI with dual voltage supply.Simulation of integrated circuits with wear-out effects.Design of digital integrated circuits from gate-level description to post-layout simulation using Mentor Graphics and Synopsys Design Compiler.Software development (C++) of a Static Timing Analysis tool for VLSI digital circuits considering aging.Analysis of temperature and executed workloads impact on digital circuit’s lifetime.Exploration of a… Show more Thesis Title: Robust aging circuits of NBTI with dual voltage supply.Simulation of integrated circuits with wear-out effects.Design of digital integrated circuits from gate-level description to post-layout simulation using Mentor Graphics and Synopsys Design Compiler.Software development (C++) of a Static Timing Analysis tool for VLSI digital circuits considering aging.Analysis of temperature and executed workloads impact on digital circuit’s lifetime.Exploration of a methodology of gates selection to operate with low VDD power supply to improve the digital circuit’s lifetime. Show less

Universidad Distrital Francisco José de Caldas
2002 - 2008Bachelor of Engineering - BE Electronics EngineeringProject Title: Implementation of inverse neural control To VSC (Voltage Source Converter)converter for active and reactive power flow.Description: An inverse neuronal control is developed for a VCS converter for a 3.5 kVA load.The neural network is trained to control the active and reactive power flows by controlling theamplitude variation of the input voltage and the phase shift between the voltage and currentinput signals, respectively.
Experience

SYMTEK
Mar 2010 - Sept 2012Senior Customer Service EngineerProvision of equipment service to X-Ray fluorescence spectrometry, X-Ray diffraction and optical emission to clients (Cement, Iron and Steel manufacturers, and Oil exploitation in South America and Central America).Provision of services to sample preparation equipment by fusion and pressing.Provision of services to fluorescence X-ray fluorescence spectrometry equipment.Customer assistance service in the previous techniques and equipment via Remote (help desk).Presentation of basic courses in line care for spectrometers, sample preparation and X-ray fluorescence. Show less

LIRMM
Aug 2018 - Aug 2019Internship ExperienceResearch in resistive open defects impact in digital cells designed with FinFET technology.Characterization of defective FinFET cells taking into account the different locations in which defects may occur due to the muti-fin/multi-finger topologies.Development of a model of the delay of the FinFET cells with resistive open defects based on RC networks.Development of a model of the delay of the FinFET cells with resistive open defects taking into account process variations based on RC networks. Show less

Intel Corporation
Apr 2021 - Apr 2023System validation Engineer
Synopsys Inc
Apr 2023 - nowStaff Solutions EngineerDFT and ATPG new product development.
Licenses & Certifications
- View certificate

Certificado de Código de Honor de edX para el curso Computation Structures - Part 1: Digital Circuits
EdXMay 2015
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