Angel Alvarez Ruiz

Experience

• 

  Universidad de Cantabria

  Dec 2015 - Jul 2016

  Research Intern

  HW-SW co-design for acceleration of C++ and OpenCV based video processing applications. The hardware was designed using high-level synthesis (HLS) and integrated in a Linux system over the Xilinx Zynq SoC platform, leading to an effective speed-up of the target application.

• 

  Universidad de Cantabria

  Jan 2018 - Nov 2019

  Worked on parallel programming and code acceleration (offloading) in heterogeneous platforms which combine CPUs with accelerators such as GPUs and FPGAs. This European Research Project (FitOptiVis) involved some industrial partners, such as Philips, Nokia and Thales Alenia Space. Code performance analysis (BER/CER) through C/MATLAB models and hardware implementation of a Non-Binary LDPC decoder for space applications using VHDL. The design was particularized for a space-certified Virtex-5QV FPGA and highly area-optimized.

  • Researcher | Hardware-Software Co-Design

    Dec 2018 - Nov 2019

  • Researcher | Channel Coding & Hardware Architectures

    Jan 2018 - Nov 2018
• 

  MaxLinear

  Nov 2019 - now

  Working into a great team responsible for industry-leading Integrated Circuits targeting next-gen Wireless Communications. Involved in chip/subsystem architecture, digital design, integration, initial verification, FPGA prototyping, bringing the chip to production and post silicon validation.

  • Staff Digital IC Design Engineer

    Apr 2024 - now

  • Senior ASIC Design Engineer

    Nov 2020 - Apr 2024

  • ASIC Design Engineer

    Nov 2019 - Nov 2020