Experience

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  Maxim integrated

  Jan 2004 - Oct 2010

  Product engineer

  Test and Product Engineer (Jan. 2004 to Sep. 2010)Supported laser trimmed products while leading a laser maintenance team in maintaining 29 various laser systems (GSI M310, ESI 2050 and Teradyne M118). While my team does most of the routine work, I focus on process, software and hardware improvements for the laser systems.Accomplishments: - Supported the processing of blanket-trim lots by acting as the key person to disposition trim issues and resolve laser problems. - Calibration process optimizations. Automated the gathering, failure flagging and archiving of the calibration data. - Product transfers and production ramp-up. - Contributed in recruitment efforts particularly in the interviewing and screening of engineers and technicians. Provided sound recommendations to the managers regarding each applicant. Show less

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  On semiconductor

  Oct 2010 - Aug 2017

  Senior product and test engineer

  Wafer Sort and Final Test Product Engineer (Oct 2010 to Aug 2017)Pioneered IC testing and trimming in the Wafer Sort line of the Cebu Facility. - Technical and team lead. Trainor and mentor to new engineers. - - Ensure all manufacturing requirements are met in preparation for volume ramp up. - - Meet quality, yield and cycle time requirements of Cebu site. - New product introduction from qualification to volume ramp-up - Lead super user for Yield Management System (exensio-Yield). Create analysis templates, train users and review database data integrity.Accomplishments: - Qualified 30+ core products from the US, Malaysia and Korea. Met yield and parametric correlation criteria within tight project timelines. - Migrated 10+ products from MCT and ETS-564 to the ETS-364. - FT UIL loss reduction - Qualification & release of “High-current Wafer-level UIL testing” in Cebu. - Presented in the 2012 Fairchild Back-end technical sharing (Penang, Malaysia). - - Presentation: “Q/V parameter – Screening high RDSon dice in Wafer Sort” - Improved wafer sort yield of FDZ191P DMOS CSP device from 90% to 96% by correlating wafer level RDSon to singulated RDSon. Show less

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  Globalfoundries

  Aug 2017 - Sept 2020

  Senior product engineer

  Product engineer for PMIC devies in the 0.18um tech node. Manage yield and work with fab process engineers for improvement. - Translate test data to actionable information for fab process engineers. - Plan and request failure analysis activities and interpret results. - Analyze test and yield data to be able to provide sound recommendations to management. Tools used are KLArity ACE, Spotfire and JMP. - Data analysis automation projects. Recently completed a wafermap cluster detection project using R and the DBSCAN library. Currently working on Fab wide yield database and report automation. Show less

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  Stmicroelectronics

  Sept 2020 - now

  Characterization engineer

  Test and Characterization Engineer handling new product development of mixed signal ASICs. - Bench testing for design validation and IP characterization - Test HW design