Experience

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  Msme-technology development centre (ppdcagra)

  Dec 2018 - Jan 2019

  Education training
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  Damodar valley corporation

  Jul 2019 - Aug 2019

  Education training
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  Durgapur steel plant

  Dec 2019 - Jan 2020

  Education training
• 

  Damodar valley corporation

  Aug 2020 - Aug 2020

  Education training
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  Qualcomm

  Jul 2022 - now

  1 .Responsible for Cache coherency verification for core as well as cluster in CPU.Worked in cache architecture management and cache design.verification of L2 and L3 cache level sizes and their respective read write transactions. 2. Verification of CPU subsystem testbus, managing and verification of TB of the TL. Verification of correct forces of all the signals, proper functionality of the checkers and MIBU assertions involved by fsdb waveform dump. Verification of testbus muxing of LLM,IPM ,PLL and other components of CPU sub system3. NT GLS - gateid creation, force file generation (with and without simulation) . Verification of sanity in GLS environment and checking if boot fsm is complete. Low power architecture checks , scan chain insertion and verification of scanflops , internal clocks , low power signals so that X propagation can be avoided. Forcing resets in NRF so that X does not corrupt the design.4. PAGLS bringup. Creation of force files based on separate power domains, usage of proper UPF and DB . PA Sanity verification and corresponding verification of correct bootflow in PA scenarios. Show less

  • CPU DV ENGINEER

    Jul 2023 - now

  • CPU DV engineering intern

    Jul 2022 - Jul 2023