Experience

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  Indian institute of technology, madras

  Feb 2023 - Jun 2023

  Project intern

   Project Overview:• Designed and developed a communication protocol tailored for real-time embedded system processors.• Focused on implementing the AXI Stream protocol to facilitate modern-day data transfers, specifically for Shakti processors at RISE Lab.• The project focused on developing a robust communication protocol to facilitate seamless data transfer within processors. Implementation:• Utilized Bluespec System Verilog (BSV) supported by an open-source Bluespec compiler for protocol implementation.• Generated synthesizable Register Transfer Level (RTL) code using the Bluespec Compiler.• Employed Verilator for fast simulation performance and visualization of waveforms.• Utilized Vivado as a backend tool for synthesizing and implementing the RTL into specific FPGA or SoC target devices. Architecture:• Implemented using AXI5 stream interfaces for efficient data transfer.• Integrated multiple transactors, including masters and slaves, to manage data flow.• Incorporated clock division, reset, and memory interface generation modules for comprehensive functionality. Impact:• Improved performance and efficiency of modern processors through optimized compatibility and interoperability through standardized data transfer methods. Key Contributions:• Developed a robust communication protocol to enhance processor performance.• Ensured efficient signal connectivity and power utilization within the design.Conducted comprehensive verification to validate data transmission accuracy. Tools Used:Bluespec System Verilog (BSV), Bluespec Compiler, Verilator, Vivado. Linux-Ubuntu Show less