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Arun Appukuttan

Arun Appukuttan

Design Engineer

Followers of Arun Appukuttan1000 followers
location of Arun AppukuttanBengaluru, Karnataka, India

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  • Timeline

  • Skills

    Vlsi
    Verilog
    Timing closure
    Logic synthesis
    Asic
    Soc
    Static timing analysis
    Functional verification
    Spyglass
    Tcl
    Operating systems
    Vhdl
    Shell scripting
    Primetime
    Integrated circuit design
    Perl
    Compilers
    Unix
    Amba ahb

  • About me

    SUMMARY: Around 9 years experience in IC DESIGN. Currently employed with Open-Silicon, from August 2010 till date.  Experience in creating the Synthesis and Timing Closure Flow to be used in Cadence tools.  Experience in creating Synthesis and Timing sign-off checklists.  Expertise in Timing closure of block and top level using Cadence tool set.  Expertise in Synthesis and Logic Equivalence Checking using Cadence tool set.  Experience in Power Estimation and Low Power Implementation and Low Power Verification using CLP checks.  Exposure of Design for Test (DFT) and Physical Design (PD) Flows.

  • Education

    • 2008 Dayananda Sagar College of Engineering VTU

      -
      B.E ECE

      Course Year Institution Board/ University Percentage of marks

    • SSLC 2002 RJS High School Karnataka State

      -

    • Dayananda sagar college of Engineering

      2004 - 2008
      B. E Electronics & Communication

    • Indian Institute of Management Bangalore

      2014 - 2016
      Master of Business Administration (M.B.A.) Post Graduate Program in Enterprise Management (PGPEM)

      Activities and Societies: Secretary - Student Association Council (SAC) -2015

  • Experience

    • Sasken Technologies Limited

      Jul 2008 - Jul 2010
      Design Engineer

    • Open-Silicon, Inc.

      Aug 2010 - now

      Currenetly working on Synthesis , Logic Equivalence Checking and Static Timing Analysis activities .

      • Senior Technical Solutions Manager

        Jan 2021 - now

      • Technical Solutions Manager

        Mar 2018 - Jul 2021

      • Technical Solutions Lead

        Jan 2017 - Jul 2021

      • Asic Design Engineer

        Aug 2010 - Dec 2016

  • Licenses & Certifications